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Research Output

  • 1613 Citations
  • 20 h-Index
  • 68 Conference contribution
  • 36 Article
  • 1 Chapter
2011

Geyser-2: The second prototype CPU with fine-grained run-time power gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 87-88 2 p. 5722310

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 Jan 26, In : 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011. p. 87-88

Research output: Contribution to journalArticle

10 Citations (Scopus)

On-chip detection methodology for break-even time of power gated function units

Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H. & Nakamura, H., 2011, Proceedings of the International Symposium on Low Power Electronics and Design. p. 241-246 6 p. 5993643

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Performance, area, and power evaluations of ultrafine-grained run-time power-gating routers for CMPs

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2011 Apr, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 4, p. 520-533 14 p., 5737865.

Research output: Contribution to journalArticle

28 Citations (Scopus)

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H. & Kondo, M., 2011, IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 5890918

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
1 Citation (Scopus)
2010

Adaptive power gating for function units in a microprocessor

Usami, K., Hashida, T., Koyama, S., Yamamoto, T., Ikebuchi, D., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2010, Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. p. 29-37 9 p. 5450407

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2010, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 369-370 2 p. 5419857

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2010 Jan 18, In : Default journal. p. 369-370

Research output: Contribution to journalArticle

4 Citations (Scopus)

Ultra fine-grained run-time power gating of on-chip routers for CMPs

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2010, NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip. p. 61-68 8 p. 5507560

Research output: Chapter in Book/Report/Conference proceedingConference contribution

45 Citations (Scopus)
2009

Cache controller design on ultra low leakage embedded processors

Lei, Z., Xu, H., Seki, N., Yoshiki, S., Hasegawa, Y., Usami, K. & Amano, H., 2009, In : Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 5455 LNCS, p. 171-182 12 p.

Research output: Contribution to journalArticle

Design and implementation of fine-grain power gating with ground bounce suppression

Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., Seki, N., Amano, H., Namiki, M., Imai, M., Kondo, M. & Nakamura, H., 2009, Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. p. 381-386 6 p. 4749703

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with Fine Grain Runtime Power Gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2009 Nov 16, In : IEEE Asian Solid-State Circuits Conference (A-SSCC) 2009. p. 281-284

Research output: Contribution to journalArticle

33 Citations (Scopus)

Implementation and evaluation of fine-grain run-time power gating for a multiplier

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H. & Nakamura, H., 2009, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 7-10 4 p. 5166253

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)
2008

A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Toshihiro Kashima, K., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M. & Nakamura, H., 2008, 26th IEEE International Conference on Computer Design 2008, ICCD. p. 612-617 6 p. 4751924

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Citations (Scopus)

Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

Shirai, T. & Usami, K., 2008, 2008 International SoC Design Conference, ISOCC 2008. Vol. 1. 4815634

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K. & Amano, H., 2008, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 329-332 4 p. 4762410

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Power Gating for Ultra-low Leakage: Physics; Design; and Analysis

F.Jerry, F. J., K.Choi, K. C., K.Usami, K. U. & Usami, K., 2008 Mar 3, In : Design; Automation and Test in Europe 2008 (DATE'08).

Research output: Contribution to journalArticle

Power-Switch Clustering Method for Static Timing Analysis

T.Hashida, T. H., K.Usami, K. U. & Usami, K., 2008 Jul 8, In : 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08). p. 217-220

Research output: Contribution to journalArticle

2007

Overview on low power SoC design technology

Usami, K., 2007, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 634-636 3 p. 4196103

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)
2006

A design approach for fine-grained run-time power gating using locally extracted sleep signals

Usami, K. & Ohkubo, N., 2006, IEEE International Conference on Computer Design, ICCD 2006. p. 155-161 7 p. 4380809

Research output: Chapter in Book/Report/Conference proceedingConference contribution

64 Citations (Scopus)

Delay modeling and static timing analysis for MTCMOS circuits

Ohkubo, N. & Usami, K., 2006, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Vol. 2006. p. 570-575 6 p. 1594746

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Leakage in Nanometer CMOS Technologies -Methodologies for Power Gating

Usami, K., Sakurai, T. & authors., . M., 2006 Oct 1, In : Default journal. p. 77-104

Research output: Contribution to journalArticle

2005

Analysis on MTCMOS Circuits based on Lumped RC Model for Virtual Ground Line

K.Usami, K. U., N.Ohkubo, N. O., M.Shirakawa, M. S. & Usami, K., 2005 Oct 1, In : IEEE International SoC Design Conference 2005 (ISOCC'05). p. 116-119

Research output: Contribution to journalArticle

2004

A scheme to reduce active leakage power by detecting state transitions

Usami, K. & Yoshioka, H., 2004, Midwest Symposium on Circuits and Systems. Vol. 1.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)
5 Citations (Scopus)
2002

Automated selective multi-threshold design for ultra-low standby applications

Usami, K., Kawabe, N., Koizumi, M., Seta, K. & Furusawa, T., 2002, Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers. p. 202-206 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

60 Citations (Scopus)

Code coverage-based power estimation techniques for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2002 Oct, In : Journal of Circuits, Systems and Computers. 11, 5, p. 557-574 18 p.

Research output: Contribution to journalArticle

4 Citations (Scopus)

Selective multi-threshold technique for high-performance and low-standby applications

Usami, K., Kawabe, N., Koizumi, M., Seta, K. & Furusawa, T., 2002 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2667-2673 7 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
2000

Function-level power estimation methodology for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2000, Proceedings - Design Automation Conference. IEEE, p. 810-813 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

66 Citations (Scopus)

Low-power design methodology and applications utilizing dual supply voltages

Usami, K. & Igarashi, M., 2000, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. p. 123-128 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Citations (Scopus)

Low-power technique for on-chip memory using biased partitioning and access concentration

Kawabe, N. & Usami, K., 2000, Proceedings of the Custom Integrated Circuits Conference. IEEE, p. 275-278 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)
1998

60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Tsuboi, Y., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Momose, H. & Usami, K., 1998, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Anon (ed.). IEEE, p. 36-37 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Kuroda, T. & Furuyama, T., 1998 Nov, In : IEEE Journal of Solid-State Circuits. 33, 11, p. 1772-1778 7 p.

Research output: Contribution to journalArticle

72 Citations (Scopus)

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Igarashi, M., Minami, F., Ishikawa, T., Kanazawa, M., Ichida, M. & Nogami, K., 1998 Mar, In : IEEE Journal of Solid-State Circuits. 33, 3, p. 463-471 9 p.

Research output: Contribution to journalArticle

192 Citations (Scopus)

Clock-gating method for low-power LSI design

Kitahara, T., Minami, F., Ueda, T., Usami, K., Nishio, S., Murakata, M. & Mitsuhashi, T., 1998, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE, p. 307-312 6 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

12 Citations (Scopus)

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Takahashi, M., Hamada, M., Arakida, H., Terazawa, T. & Kuroda, T., 1998, Proceedings - Design Automation Conference. IEEE, p. 483-488 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

29 Citations (Scopus)

Top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme

Hamada, M., Takahashi, M., Arakida, H., Chiba, A., Terazawa, T., Ishikawa, T., Kanazawa, M., Igarashi, M., Usami, K. & Kuroda, T., 1998, Proceedings of the Custom Integrated Circuits Conference. Anon (ed.). IEEE, p. 495-498 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

78 Citations (Scopus)
1997

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Nogami, K., Igarashi, M., Minami, F., Kawasaki, Y., Ishikawa, T., Kanazawa, M., Aoki, T., Takano, M., Mizuno, C., Ichida, M., Sonoda, S., Takahashi, M. & Hatanaka, N., 1997, Proceedings of the Custom Integrated Circuits Conference. IEEE, p. 131-134 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Citations (Scopus)

Low-power design method using multiple supply voltages

Igarashi, M., Usami, K., Nogami, K., Minami, F., Kawasaki, Y., Aoki, T., Takano, M., Mizuno, C., Lshikawa, T., Kanazawa, M., Sonoda, S., Ichida, M. & Hatanaka, N., 1997, International Symposium on Low Power Electronics and Design, Digest of Technical Papers. Piscataway, NJ, United States: IEEE, p. 36-41 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

51 Citations (Scopus)
1996

Low-power design technique for ASICs by partially reducing supply voltage

Usami, K., Ishikawa, T., Kanazawa, M. & Kotani, H., 1996, Proceedings of the Annual IEEE International ASIC Conference and Exhibit. Meindl, J. D., Mukund, P. R., Gabara, T. & Sridhar, R. (eds.). p. 301-304 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)
1995

Clustered voltage scaling technique for low-power design

Usami, K. & Horowitz, M., 1995, Proceedings of the International Symposium on Low Power Design. New York, NY, United States: ACM, p. 3-8 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

322 Citations (Scopus)
1991

Hierarchical symbolic design methodology for large-scale data paths

Usami, K., Sugeno, Y., Matsumoto, N. & Mori, S., 1991 Mar, In : IEEE Journal of Solid-State Circuits. 26, 3, p. 381-385 5 p.

Research output: Contribution to journalArticle

1990

Datapath generator based on gate-level symbolic layout

Matsumoto, N., Watanabe, Y., Usami, K., Sugeno, Y., Hatada, H. & Mori, S., 1990, 27th ACM/IEEE Design Automation Conference. Proceedings 1990. Piscataway, NJ, United States: Publ by IEEE, p. 388-393 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)