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Research Output

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yoshida, Y., Usami, K. & Amano, H., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 148-149 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

Koizumi, Y., Amano, H., Matsutani, H., Miura, N., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012 Dec 1, FPT 2012 - 2012 International Conference on Field-Programmable Technology. p. 293-296 4 p. 6412150. (FPT 2012 - 2012 International Conference on Field-Programmable Technology).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)
5 Citations (Scopus)

Dynamic VDD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

Yamamoto, T., Hironaka, K., Hayakawa, Y., Kimura, M., Amano, H. & Usami, K., 2011 Apr 4, Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings. p. 230-241 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 6578 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Efficient leakage power saving by sleep depth controlling for multi-mode power gating

Takeda, S., Miwa, S., Usami, K. & Nakamura, H., 2012 Jul 16, Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012. p. 625-632 8 p. 6187558. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami, K., Akaike, J., Akiba, S., Kudo, M., Amano, H., Ikezoe, T., Hiraga, K., Shuto, Y. & Yagami, K., 2018 Nov 15, Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., p. 91-98 8 p. 8537701

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Fine-grained power control using a multi-voltage variable pipeline router

Nakamura, T., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2012 Dec 1, p. 59-66. 8 p.

Research output: Contribution to conferencePaper

4 Citations (Scopus)

Fine-grained run-tume power gating through co-optimization of circuit, architecture, and system software design

Nakamura, H., Wang, W., Ohta, Y., Usami, K., Amano, H., Kondo, M. & Namiki, M., 2013 Apr, In : IEICE Transactions on Electronics. E96-C, 4, p. 404-412 9 p.

Research output: Contribution to journalArticle

Floorplan driven architecture and high-level synthesis algorithm for dynamic multiple supply voltages

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, p. 2597-2611 15 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Foreword

Usami, K., 2013 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, 1 p.

Research output: Contribution to journalEditorial

Foreword: Special section on VLSI design and CAD algorithms

Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. & 17 others, Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S. I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M. & Watanabe, T., 2014 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2366 1 p.

Research output: Contribution to journalArticle

Function-level power estimation methodology for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2000 Jan 1, In : Proceedings-Design Automation Conference. p. 810-813 4 p.

Research output: Contribution to journalArticle

66 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyamat, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2009 Dec 1, Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009. p. 281-284 4 p. 5357257. (Proceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2010 Apr 28, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 369-370 2 p. 5419857. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2010 Jan 18, In : Default journal. p. 369-370

Research output: Contribution to journalArticle

4 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with Fine Grain Runtime Power Gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2009 Nov 16, In : IEEE Asian Solid-State Circuits Conference (A-SSCC) 2009. p. 281-284

Research output: Contribution to journalArticle

33 Citations (Scopus)

Geyser-2: The second prototype CPU with fine-grained run-time power gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 Mar 28, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. p. 87-88 2 p. 5722310. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 Jan 26, In : 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011. p. 87-88

Research output: Contribution to journalArticle

10 Citations (Scopus)

Hierarchical symbolic design methodology for large-scale datapaths

Usami, K., Sugeno, Y., Matsumoto, N. & Mori, S., 1990 Dec 1, In : Proceedings of the Custom Integrated Circuits Conference.

Research output: Contribution to journalConference article

1 Citation (Scopus)

Hierarchical Symbolic Design Methodology for Large-Scale Data Paths

Usami, K., Sugeno, Y., Matsumoto, N. & Mori, S., 1991 Mar, In : IEEE Journal of Solid-State Circuits. 26, 3, p. 381-385 5 p.

Research output: Contribution to journalArticle

Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

Shirai, T. & Usami, K., 2008 Dec 1, 2008 International SoC Design Conference, ISOCC 2008. p. I310-I313 4815634. (2008 International SoC Design Conference, ISOCC 2008; vol. 1).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Implementation and evaluation of fine-grain run-time power gating for a multiplier

Usami, K., Nakata, M., Shirai, T., Takeda, S., Seki, N., Amano, H. & Nakamura, H., 2009 Dec 1, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 7-10 4 p. 5166253. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Leakage in Nanometer CMOS Technologies -Methodologies for Power Gating

Usami, K., Sakurai, T. & authors., . M., 2006 Oct 1, In : Default journal. p. 77-104

Research output: Contribution to journalArticle

Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Saito, Y., Shirai, T., Nakamura, T., Nishimura, T., Hasegawa, Y., Tsutsumi, S., Kashima, T., Nakata, M., Takeda, S., Usami, K. & Amano, H., 2008 Dec 1, Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008. p. 329-332 4 p. 4762410. (Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2018 Mar 7, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-March. p. 1-3 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2017 Dec 13, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 8203473

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2019 Jan 1, VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Revised and Extended Selected Papers. Monteiro, J., Elfadel, I. A. M., Sonza Reorda, M., Ugurdag, H. F., Maniatakos, M. & Reis, R. (eds.). Springer New York LLC, p. 1-21 21 p. (IFIP Advances in Information and Communication Technology; vol. 500).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Low-power design methodology and applications utilizing dual supply voltages

Usami, K. & Igarashi, M., 2000 Dec 1, Proceedings of the 2000 Asia and South Pacific Design Automation Conference, ASP-DAC 2000. p. 123-128 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

30 Citations (Scopus)

Low-power design method using multiple supply voltages

Igarashi, M., Usami, K., Nogami, K., Minami, F., Kawasaki, Y., Aoki, T., Takano, M., Mizuno, C., Lshikawa, T., Kanazawa, M., Sonoda, S., Ichida, M. & Hatanaka, N., 1997 Jan 1, p. 36-41. 6 p.

Research output: Contribution to conferencePaper

52 Citations (Scopus)

Low-power design technique for ASICs by partially reducing supply voltage

Usami, K., Ishikawa, T., Kanazawa, M. & Kotani, H., 1996 Jan 1, In : Proceedings of the Annual IEEE International ASIC Conference and Exhibit. p. 301-304 4 p.

Research output: Contribution to journalConference article

24 Citations (Scopus)

Low-power technique for on-chip memory using biased partitioning and access concentration

Kawabe, N. & Usami, K., 2000 Jan 1, In : Proceedings of the Custom Integrated Circuits Conference. p. 275-278 4 p.

Research output: Contribution to journalConference article

6 Citations (Scopus)

Measurement of the minimum energy point in Silicon on Thin-BOX(SOTB) and bulk MOSFET

Nakamura, S., Kawasaki, J., Kumagai, Y. & Usami, K., 2015 Mar 18, EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc., p. 193-196 4 p. 7063746

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Multi-voltage variable pipeline routers with the same clock frequency for low-power network-on-chips systems

Ahmed, A. B., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2016 Aug 1, In : IEICE Transactions on Electronics. E99C, 8, p. 909-917 9 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

Usami, K., Akiba, S., Amano, H., Ikezoe, T., Hiraga, K., Suzuki, K. & Kanda, Y., 2020 Apr, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9097630. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Kudo, M. & Usami, K., 2017 Oct 10, NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium. Institute of Electrical and Electronics Engineers Inc., 8064472. (NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

On-chip detection methodology for break-even time of power gated function units

Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H. & Nakamura, H., 2011 Sep 19, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 241-246 6 p. 5993643. (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Optimized design method for full-custom microprocessors

Usami, K. & Iwamura, J., 1989 Dec 1, In : Proceedings of the Custom Integrated Circuits Conference. p. 19.5.1-19.5.5 5726257.

Research output: Contribution to journalConference article

1 Citation (Scopus)

Overview on low power SoC design technology

Usami, K., 2007 Dec 1, Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. p. 634-636 3 p. 4196103. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Performance, area, and power evaluations of ultrafine-grained run-time power-gating routers for CMPs

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2011 Apr 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 4, p. 520-533 14 p., 5737865.

Research output: Contribution to journalArticle

29 Citations (Scopus)

Power gating for FDSOI using dynamically body-biased power switch

Kumagai, Y., Kudo, M. & Usami, K., 2015 Mar 18, EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc., p. 221-224 4 p. 7063813

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Power Gating for Ultra-low Leakage: Physics; Design; and Analysis

F.Jerry, F. J., K.Choi, K. C., K.Usami, K. U. & Usami, K., 2008 Mar 3, In : Design; Automation and Test in Europe 2008 (DATE'08).

Research output: Contribution to journalArticle

Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET

Okuhara, H., Fujita, Y., Usami, K. & Amano, H., 2016 Dec 30, (Accepted/In press) In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Research output: Contribution to journalArticle

10 Citations (Scopus)

Power-Switch Clustering Method for Static Timing Analysis

T.Hashida, T. H., K.Usami, K. U. & Usami, K., 2008 Jul 8, In : 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08). p. 217-220

Research output: Contribution to journalArticle

Selective multi-threshold technique for high-performance and low-standby applications

Usami, K., Kawabe, N., Koizumi, M., Seta, K. & Furusawa, T., 2002 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2667-2673 7 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

Single Supply Level Shifter Circuit using body-bias

Takeyoshi, Y. & Usami, K., 2019 Jun, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 8793384. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H. & Kondo, M., 2011 Jul 18, IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 5890918. (IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
1 Citation (Scopus)