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2017
2016

An operating system guided fine-grained power gating control based on runtime characteristics of applications

Koshiba, A., Sato, M., Usami, K., Amano, H., Sakamoto, R., Kondo, M., Nakamura, H. & Namiki, M., 2016 Aug 1, In : IEICE Transactions on Electronics. E99C, 8, p. 926-935 10 p.

Research output: Contribution to journalArticle

Multi-voltage variable pipeline routers with the same clock frequency for low-power network-on-chips systems

Ahmed, A. B., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2016 Aug 1, In : IEICE Transactions on Electronics. E99C, 8, p. 909-917 9 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET

Okuhara, H., Fujita, Y., Usami, K. & Amano, H., 2016 Dec 30, (Accepted/In press) In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Research output: Contribution to journalArticle

10 Citations (Scopus)
2015

A fine-grained power gating control on linux monitoring power consumption of processor functional units

Koshiba, A., Wada, M., Sakamoto, R., Sato, M., Kosaka, T., Usami, K., Amano, H., Kondo, M., Nakamura, H. & Namiki, M., 2015 Jul 1, In : IEICE Transactions on Electronics. E98C, 7, p. 559-568 10 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

An energy-efficient floorplan driven high-level synthesis algorithm for multiple clock domains design

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2015 Jul 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1376-1391 16 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Ishibashi, K., Sugii, N., Kamohara, S., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2015 Jul 1, In : IEICE Transactions on Electronics. E98C, 7, p. 536-543 8 p.

Research output: Contribution to journalArticle

17 Citations (Scopus)
2014

Foreword: Special section on VLSI design and CAD algorithms

Yamada, A., Higami, Y., Takagi, K., Amagasaki, M., Ikeda, M., Ishihara, T., Ito, K., Usami, K., Okada, K., Kajihara, S., Kaneko, M., Kawaguchi, H., Kimura, S., Kurokawa, A., Shibata, Y., Seto, K., Song, T., Takashima, Y., Takahashi, A., Takenaka, T. & 17 others, Togawa, N., Tomiyama, H., Nakatake, S., Nakamura, Y., Hashimoto, M., Hamaguchi, K., Higuchi, H., Hirose, T., Fukuda, D., Matsumoto, T., Miura, Y., Minato, S. I., Minami, F., Yamashita, S., Yuminaka, Y., Yoshikawa, M. & Watanabe, T., 2014 Dec 1, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E97A, 12, p. 2366 1 p.

Research output: Contribution to journalArticle

2013

A scalable 3D heterogeneous multicore with an inductive ThruChip interface

Miura, N., Koizumi, Y., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 Nov 1, In : IEEE Micro. 33, 6, p. 6-15 10 p., 6684194.

Research output: Contribution to journalArticle

21 Citations (Scopus)

Fine-grained run-tume power gating through co-optimization of circuit, architecture, and system software design

Nakamura, H., Wang, W., Ohta, Y., Usami, K., Amano, H., Kondo, M. & Namiki, M., 2013 Apr, In : IEICE Transactions on Electronics. E96-C, 4, p. 404-412 9 p.

Research output: Contribution to journalArticle

Floorplan driven architecture and high-level synthesis algorithm for dynamic multiple supply voltages

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, p. 2597-2611 15 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)
2011

Cool mega-arrays: Ultralow-power reconfigurable accelerator chips

Ozaki, N., Yasuda, Y., Izawa, M., Saito, Y., Ikebuchi, D., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011 Nov 1, In : IEEE Micro. 31, 6, p. 6-18 13 p., 6060791.

Research output: Contribution to journalArticle

39 Citations (Scopus)

Design and implementation fine-grained power gating on microprocessor functional units

Lei, Z., Ikebuchi, D., Usami, K., Namiki, M., Kondo, M., Nakamura, H. & Amano, H., 2011 Dec 5, In : IPSJ Transactions on System LSI Design Methodology. 4, p. 182-192 11 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 Jan 26, In : 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011. p. 87-88

Research output: Contribution to journalArticle

10 Citations (Scopus)

Performance, area, and power evaluations of ultrafine-grained run-time power-gating routers for CMPs

Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2011 Apr 1, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 4, p. 520-533 14 p., 5737865.

Research output: Contribution to journalArticle

29 Citations (Scopus)
1 Citation (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2010 Jan 18, In : Default journal. p. 369-370

Research output: Contribution to journalArticle

4 Citations (Scopus)

Geyser-1: A MIPS R3000 CPU core with Fine Grain Runtime Power Gating

D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2009 Nov 16, In : IEEE Asian Solid-State Circuits Conference (A-SSCC) 2009. p. 281-284

Research output: Contribution to journalArticle

33 Citations (Scopus)

Power Gating for Ultra-low Leakage: Physics; Design; and Analysis

F.Jerry, F. J., K.Choi, K. C., K.Usami, K. U. & Usami, K., 2008 Mar 3, In : Design; Automation and Test in Europe 2008 (DATE'08).

Research output: Contribution to journalArticle

Power-Switch Clustering Method for Static Timing Analysis

T.Hashida, T. H., K.Usami, K. U. & Usami, K., 2008 Jul 8, In : 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08). p. 217-220

Research output: Contribution to journalArticle

2006

Leakage in Nanometer CMOS Technologies -Methodologies for Power Gating

Usami, K., Sakurai, T. & authors., . M., 2006 Oct 1, In : Default journal. p. 77-104

Research output: Contribution to journalArticle

2005

Analysis on MTCMOS Circuits based on Lumped RC Model for Virtual Ground Line

K.Usami, K. U., N.Ohkubo, N. O., M.Shirakawa, M. S. & Usami, K., 2005 Oct 1, In : IEEE International SoC Design Conference 2005 (ISOCC'05). p. 116-119

Research output: Contribution to journalArticle

2004
5 Citations (Scopus)
2002

Code coverage-based power estimation techniques for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2002 Oct 1, In : Journal of Circuits, Systems and Computers. 11, 5, p. 557-574 18 p.

Research output: Contribution to journalArticle

4 Citations (Scopus)

Selective multi-threshold technique for high-performance and low-standby applications

Usami, K., Kawabe, N., Koizumi, M., Seta, K. & Furusawa, T., 2002 Dec, In : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2667-2673 7 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
2000

Function-level power estimation methodology for microprocessors

Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2000 Jan 1, In : Proceedings-Design Automation Conference. p. 810-813 4 p.

Research output: Contribution to journalArticle

66 Citations (Scopus)
1998

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Kuroda, T. & Furuyama, T., 1998 Nov 1, In : IEEE Journal of Solid-State Circuits. 33, 11, p. 1772-1778 7 p.

Research output: Contribution to journalArticle

72 Citations (Scopus)

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Usami, K., Igarashi, M., Minami, F., Ishikawa, T., Kanazawa, M., Ichida, M. & Nogami, K., 1998 Mar 1, In : IEEE Journal of Solid-State Circuits. 33, 3, p. 463-472 10 p.

Research output: Contribution to journalArticle

196 Citations (Scopus)
1991

Hierarchical Symbolic Design Methodology for Large-Scale Data Paths

Usami, K., Sugeno, Y., Matsumoto, N. & Mori, S., 1991 Mar, In : IEEE Journal of Solid-State Circuits. 26, 3, p. 381-385 5 p.

Research output: Contribution to journalArticle

1989

Design of a 32-bit Microprocessor, TX1

Tokumaru, T., Masuda, E., Usami, K., Miyata, M., Iwamura, J. & Hori, C., 1989 Aug, In : IEEE Journal of Solid-State Circuits. 24, 4, p. 938-944 7 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)