• 687 Citations
  • 14 h-Index
1983 …2019

Research output per year

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Research Output

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2019
2014

Low-power widely tunable Gm-C filter employing an adaptive DC-blocking, triode-biased MOSFET transconductor

Hori, S., Matsuno, N., Maeda, T. & Hida, H., 2014 Jan 1, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 61, 1, p. 37-47 11 p., 6547713.

Research output: Contribution to journalArticle

14 Citations (Scopus)
2012

A 2.5 kV isolation 35 kV/us CMR 250 Mbps digital isolator in standard CMOS with a small transformer driving technique

Kaeriyama, S., Uchida, S., Furumiya, M., Okada, M., Maeda, T. & Mizuno, M., 2012 Feb 1, In : IEEE Journal of Solid-State Circuits. 47, 2, p. 435-443 9 p., 6075274.

Research output: Contribution to journalArticle

38 Citations (Scopus)

A 30-MHz-2.4-GHz CMOS receiver with integrated RF filter and dynamic-range-scalable energy detector for cognitive radio systems

Kitsunezuka, M., Kodama, H., Oshima, N., Kunihiro, K., Maeda, T. & Fukaishi, M., 2012 May 1, In : IEEE Journal of Solid-State Circuits. 47, 5, p. 1084-1093 10 p., 6155617.

Research output: Contribution to journalArticle

46 Citations (Scopus)
2011

A low-IF/Zero-IF reconfigurable analog baseband ic with an I/Q imbalance cancellation scheme

Kitsunezuka, M., Tokairin, T., Maeda, T. & Fukaishi, M., 2011 Mar 1, In : IEEE Journal of Solid-State Circuits. 46, 3, p. 572-582 11 p., 5708186.

Research output: Contribution to journalArticle

22 Citations (Scopus)
2010

A 2.1-to-2.8-GHz low-phase-noise all-digital frequency synthesizer with a time-windowed time-to-digital converter

Tokairin, T., Okada, M., Kitsunezuka, M., Maeda, T. & Fukaishi, M., 2010 Dec 1, In : IEEE Journal of Solid-State Circuits. 45, 12, p. 2582-2590 9 p., 5604672.

Research output: Contribution to journalArticle

67 Citations (Scopus)

Analytical expression of quantization noise in time-to-digital converter based on the fourier series analysis

Maeda, T. & Tokairin, T., 2010 Jan 6, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 57, 7, p. 1538-1548 11 p., 5371917.

Research output: Contribution to journalArticle

6 Citations (Scopus)
2009

A widely-tunable, reconfigurable CMOS analog baseband IC for software-defined radio

Kitsunezuka, M., Hori, S. & Maeda, T., 2009 Sep 1, In : IEEE Journal of Solid-State Circuits. 44, 9, p. 2496-2502 7 p., 5226708.

Research output: Contribution to journalArticle

33 Citations (Scopus)
2006

A low-power dual-band triple-mode WLAN CMOS Transceiver

Maeda, T., Matsuno, N., Hori, S., Yamase, T., Tokairin, T., Yanagisawa, K., Yano, H., Walkington, R., Numata, K., Yoshida, N., Takahashi, Y. & Hida, H., 2006 Nov 1, In : IEEE Journal of Solid-State Circuits. 41, 11, p. 2481-2489 9 p., 1717671.

Research output: Contribution to journalArticle

28 Citations (Scopus)

Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

Maeda, T., Yano, H., Hori, S., Matsuno, N., Yamase, T., Tokairin, T., Walkington, R., Yoshida, N., Numata, K., Yanagisawa, K., Takahashi, Y., Fujii, M. & Hida, H., 2006 Feb 1, In : IEEE Journal of Solid-State Circuits. 41, 2, p. 375-382 8 p.

Research output: Contribution to journalArticle

41 Citations (Scopus)
2002

A low-noise low-IF 0.18μm CMOS receiver IC with an active on-chip channel-selection filter for 5GHz wireless applications

Yano, H., Hori, S., Maeda, T., Matsuno, N., Numata, K., Fujii, M., Yoshida, N., Takahashi, Y. & Hida, H., 2002 Oct, In : NEC Research and Development. 43, 4, p. 314-319 6 p.

Research output: Contribution to journalArticle

1999

0.21-fJ GaAs DCFL circuits using 0.2-/zm Y-shaped gate AlGaAs/InGaAs E/D-HJFETs

Wada, S., Tokushima, M., Ishikawa, M., Yoshida, N., Fujii, M. & Maeda, T., 1999 Jan 1, In : IEICE Transactions on Electronics. E82-C, 3, p. 491-496 6 p.

Research output: Contribution to journalArticle

Accurate HJFET current-voltage model including temperature dependence for a circuit simulator

Matsuno, N., Yano, H., Hida, H. & Maeda, T., 1999 May, In : Solid-State Electronics. 43, 5, p. 977-984 8 p.

Research output: Contribution to journalArticle

An Ultralow-Power-Consumption, High-Speed, GaAs 256/258 Dual-Modulus Prescaler IC

Maeda, T., Wada, S., Tokushima, M., Ishikawa, M., Yamazaki, J. & Fujii, M., 1999 Dec 1, In : IEEE Journal of Solid-State Circuits. 34, 2, p. 212-217 6 p.

Research output: Contribution to journalArticle

11 Citations (Scopus)

ECL-compatible low-power-consumption 10-Gb/s GaAs 8: 1 multiplexer and 1 : 8 demultiplexer

Yoshida, N., Fujii, M., Atsumo, T., Numata, K., Kohnq, M., Oikawa, H., Tsutsui, H. & Maeda, T., 1999 Jan 1, In : IEICE Transactions on Electronics. E82-C, 11, p. 1992-1998 7 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)
1998

0.1-μm p+-GaAs gate HJFET's fabricated using two-step dry-etching and selective MOMBE growth techniques

Wada, S., Furuhata, N., Tokushima, M., Fukaishi, M., Hida, H. & Maeda, T., 1998 Dec 1, In : IEEE Transactions on Electron Devices. 45, 6, p. 1183-1189 7 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

0.2-μm Fully-Self-Aligned Y-Shaped Gate HJFET's with Reduced Gate-Fringing Capacitance Fabricated Using Collimated Sputtering and Electroless Au-Plating

Wada, S., Tokushima, M., Fukaishi, M., Matsuno, N., Yano, H., Hida, H. & Maeda, T., 1998 Dec 1, In : IEEE Transactions on Electron Devices. 45, 8, p. 1656-1662 7 p.

Research output: Contribution to journalArticle

6 Citations (Scopus)

A 150 mW 8:1 MUX and a 170 mW 1:8 DEMUX for 2.4 Gb/s optical-fiber communication systems using n-AlGaAs/i-InGaAs HJFET's

Fujii, M., Numata, K., Maeda, T., Tokushima, M., Wada, S., Fukaishi, M. & Ishikawa, M., 1998 Dec 1, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 6, 1, p. 43-46 4 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Performance of a p-channel heterojunction fet with P+ -GaAs selectively grown contact layers for GaAs complementary ICs

Furuhata, N., Fujii, M., Asai, S., Maeda, T. & Ohno, Y., 1998 Jun, In : Solid-State Electronics. 42, 6, p. 1049-1055 7 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)
1997

An accurate HJFET capacitance-voltage model for implementation with a circuit simulator

Matsuno, N., Yano, H., Hida, H. & Maeda, T., 1997 Dec 1, In : IEEE Transactions on Electron Devices. 44, 3, p. 373-378 6 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)

Analysis of the operating-speed and power consumption of GaAs DCFL D-type flip-flops

Maeda, T., 1997 Jun, In : Solid-State Electronics. 41, 6, p. 807-811 5 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Analytical expression for operating speed of GaAs SCFL D-type flip-flops

Maeda, T. & Fujii, M., 1997 Nov, In : Solid-State Electronics. 41, 11, p. 1687-1691 5 p.

Research output: Contribution to journalArticle

3 Citations (Scopus)

Formation of an n-GaAs/n-GaAs regrowth interface without carrier depletion using electron cyclotron resonance hydrogen plasma

Niwa, T., Furuhata, N. & Maeda, T., 1997 May, In : Journal of Crystal Growth. 175-176, PART 1, p. 441-446 6 p.

Research output: Contribution to journalArticle

10 Citations (Scopus)
1996

A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps

Fujii, M., Maeda, T. & Ohno, Y., 1996 Jan 1, In : IEICE Transactions on Electronics. E79-C, 4, p. 512-516 5 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)

A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's

Maeda, T., Numata, K., Tokushima, M., Ishikawa, M., Fukaishi, M., Hida, H. & Ohno, Y., 1996 Feb 1, In : IEEE Journal of Solid-State Circuits. 31, 2, p. 240-246 7 p.

Research output: Contribution to journalArticle

4 Citations (Scopus)

An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

Maeda, T., Numata, K., Fujii, M., Tokushima, M., Wada, S., Fukaishi, M. & Ishikawa, M., 1996 Sep 1, In : IEEE Journal of Solid-State Circuits. 31, 9, p. 1361-1363 3 p.

Research output: Contribution to journalArticle

10 Citations (Scopus)

A technique for compensating for temperature variation in low-supply-voltage GaAs DCFL circuits

Maeda, T., Numata, K., Ohno, Y., Hida, H., Tokushima, M., Fukaishi, M., Ishikawa, M. & Fujii, M., 1996 Nov, In : Solid-State Electronics. 39, 11, p. 1543-1547 5 p.

Research output: Contribution to journalArticle

1991

Novel slip-free rapid thermal annealing of GaAs in vacuum with excellent uniformity and reproducibility

Kohno, M., Hida, H., Ogawa, Y., Fujii, M., Maeda, T., Ohata, K. & Tsukada, Y., 1991 Dec 1, In : Journal of Applied Physics. 69, 3, p. 1294-1299 6 p.

Research output: Contribution to journalArticle

1983

A numerical model of selective meltback morphology on InP

Pak, K., Maeda, T., Nishinaga, T., Nakamura, T. & Yasuda, Y., 1983 Dec 2, In : Journal of Crystal Growth. 65, 1-3, p. 602-606 5 p.

Research output: Contribution to journalArticle

1 Citation (Scopus)