0.1-μm double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs

Shigeki Wada, Jin Yamazaki, Masaoki Ishikawa, Tadashi Maeda

Research output: ResearchConference contribution

  • 1 Citations

Abstract

This paper describes on a novel double-deck-shaped (DDS) gate technology for 0.1-μm heterojunction-FETs (HJFETs) that have half the external gate fringing capacitance (Cfext) of conventional T-shaped gate HJFETs. By introducing a T-shaped SiO2-opening technique based on two-step dry-etching with W-film masks, we have fabricated 0.1-μm DDS gate-openings adapted to the reduction in Cfext and to the voidless-filling of gate-metals. Moreover, by using WSi-collimated sputtering and electroless Au-plating, 0.1-μm DDS WSi/Ti/Pt/Au gate HJFETs with high uniformity and reproducibility are made. Fabricated n-Al0.2Ga0.8As/ In0.15Ga0.75As HJFETs exhibit an excellent Vth standard-deviation (σVth) of 39 mV. Also, the HJFET covered with a SiO2 film shows a very high millimeter-wave performance with fT of 120 GHz and fmax of 165 GHz, due to the low Cfext. In addition, a high fT of 151 GHz and fmax of 186 GHz are obtained without a SiO2 film.

LanguageEnglish
Title of host publicationIEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Proceedings
PublisherIEEE
Pages70-73
Number of pages4
StatePublished - 1997
Externally publishedYes
EventProceedings of the 1997 19th Annual GaAs IC Symposium - Anaheim, CA, USA
Duration: 1997 Oct 121997 Oct 15

Other

OtherProceedings of the 1997 19th Annual GaAs IC Symposium
CityAnaheim, CA, USA
Period97/10/1297/10/15

Fingerprint

Field effect transistors
Heterojunctions
Capacitance
Dry etching
Electroless plating
Millimeter waves
Sputtering
Masks
Metals

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Wada, S., Yamazaki, J., Ishikawa, M., & Maeda, T. (1997). 0.1-μm double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs. In IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Proceedings (pp. 70-73). IEEE.

0.1-μm double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs. / Wada, Shigeki; Yamazaki, Jin; Ishikawa, Masaoki; Maeda, Tadashi.

IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Proceedings. IEEE, 1997. p. 70-73.

Research output: ResearchConference contribution

Wada, S, Yamazaki, J, Ishikawa, M & Maeda, T 1997, 0.1-μm double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs. in IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Proceedings. IEEE, pp. 70-73, Proceedings of the 1997 19th Annual GaAs IC Symposium, Anaheim, CA, USA, 97/10/12.
Wada S, Yamazaki J, Ishikawa M, Maeda T. 0.1-μm double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs. In IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Proceedings. IEEE. 1997. p. 70-73.
Wada, Shigeki ; Yamazaki, Jin ; Ishikawa, Masaoki ; Maeda, Tadashi. / 0.1-μm double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs. IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Proceedings. IEEE, 1997. pp. 70-73
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