0.1-μm double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs

Shigeki Wada; Jin Yamazaki; Masaoki Ishikawa; Tadashi Maeda

0.1-μm double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs

Shigeki Wada, Jin Yamazaki, Masaoki Ishikawa, Tadashi Maeda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper describes on a novel double-deck-shaped (DDS) gate technology for 0.1-μm heterojunction-FETs (HJFETs) that have half the external gate fringing capacitance (C_f^ext) of conventional T-shaped gate HJFETs. By introducing a T-shaped SiO₂-opening technique based on two-step dry-etching with W-film masks, we have fabricated 0.1-μm DDS gate-openings adapted to the reduction in C_f^ext and to the voidless-filling of gate-metals. Moreover, by using WSi-collimated sputtering and electroless Au-plating, 0.1-μm DDS WSi/Ti/Pt/Au gate HJFETs with high uniformity and reproducibility are made. Fabricated n-Al_0.2Ga_0.8As/ In_0.15Ga_0.75As HJFETs exhibit an excellent V_th standard-deviation (σV_th) of 39 mV. Also, the HJFET covered with a SiO₂ film shows a very high millimeter-wave performance with f_T of 120 GHz and f_max of 165 GHz, due to the low C_f^ext. In addition, a high f_T of 151 GHz and f_max of 186 GHz are obtained without a SiO₂ film.

Original language	English
Title of host publication	IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Proceedings
Publisher	IEEE
Pages	70-73
Number of pages	4
Publication status	Published - 1997
Externally published	Yes
Event	Proceedings of the 1997 19th Annual GaAs IC Symposium - Anaheim, CA, USA Duration: 1997 Oct 12 → 1997 Oct 15

Other

Other	Proceedings of the 1997 19th Annual GaAs IC Symposium
City	Anaheim, CA, USA
Period	97/10/12 → 97/10/15

ASJC Scopus subject areas

Engineering(all)

Cite this

@inproceedings{2b2da9eeb26a4df8bf580663be464268,

title = "0.1-μm double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs",

abstract = "This paper describes on a novel double-deck-shaped (DDS) gate technology for 0.1-μm heterojunction-FETs (HJFETs) that have half the external gate fringing capacitance (Cfext) of conventional T-shaped gate HJFETs. By introducing a T-shaped SiO2-opening technique based on two-step dry-etching with W-film masks, we have fabricated 0.1-μm DDS gate-openings adapted to the reduction in Cfext and to the voidless-filling of gate-metals. Moreover, by using WSi-collimated sputtering and electroless Au-plating, 0.1-μm DDS WSi/Ti/Pt/Au gate HJFETs with high uniformity and reproducibility are made. Fabricated n-Al0.2Ga0.8As/ In0.15Ga0.75As HJFETs exhibit an excellent Vth standard-deviation (σVth) of 39 mV. Also, the HJFET covered with a SiO2 film shows a very high millimeter-wave performance with fT of 120 GHz and fmax of 165 GHz, due to the low Cfext. In addition, a high fT of 151 GHz and fmax of 186 GHz are obtained without a SiO2 film.",

author = "Shigeki Wada and Jin Yamazaki and Masaoki Ishikawa and Tadashi Maeda",

year = "1997",

language = "English",

pages = "70--73",

booktitle = "IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Proceedings",

publisher = "IEEE",

note = "Proceedings of the 1997 19th Annual GaAs IC Symposium ; Conference date: 12-10-1997 Through 15-10-1997",

}

TY - GEN

T1 - 0.1-μm double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs

AU - Wada, Shigeki

AU - Yamazaki, Jin

AU - Ishikawa, Masaoki

AU - Maeda, Tadashi

PY - 1997

Y1 - 1997

N2 - This paper describes on a novel double-deck-shaped (DDS) gate technology for 0.1-μm heterojunction-FETs (HJFETs) that have half the external gate fringing capacitance (Cfext) of conventional T-shaped gate HJFETs. By introducing a T-shaped SiO2-opening technique based on two-step dry-etching with W-film masks, we have fabricated 0.1-μm DDS gate-openings adapted to the reduction in Cfext and to the voidless-filling of gate-metals. Moreover, by using WSi-collimated sputtering and electroless Au-plating, 0.1-μm DDS WSi/Ti/Pt/Au gate HJFETs with high uniformity and reproducibility are made. Fabricated n-Al0.2Ga0.8As/ In0.15Ga0.75As HJFETs exhibit an excellent Vth standard-deviation (σVth) of 39 mV. Also, the HJFET covered with a SiO2 film shows a very high millimeter-wave performance with fT of 120 GHz and fmax of 165 GHz, due to the low Cfext. In addition, a high fT of 151 GHz and fmax of 186 GHz are obtained without a SiO2 film.

AB - This paper describes on a novel double-deck-shaped (DDS) gate technology for 0.1-μm heterojunction-FETs (HJFETs) that have half the external gate fringing capacitance (Cfext) of conventional T-shaped gate HJFETs. By introducing a T-shaped SiO2-opening technique based on two-step dry-etching with W-film masks, we have fabricated 0.1-μm DDS gate-openings adapted to the reduction in Cfext and to the voidless-filling of gate-metals. Moreover, by using WSi-collimated sputtering and electroless Au-plating, 0.1-μm DDS WSi/Ti/Pt/Au gate HJFETs with high uniformity and reproducibility are made. Fabricated n-Al0.2Ga0.8As/ In0.15Ga0.75As HJFETs exhibit an excellent Vth standard-deviation (σVth) of 39 mV. Also, the HJFET covered with a SiO2 film shows a very high millimeter-wave performance with fT of 120 GHz and fmax of 165 GHz, due to the low Cfext. In addition, a high fT of 151 GHz and fmax of 186 GHz are obtained without a SiO2 film.

UR - http://www.scopus.com/inward/record.url?scp=0031352134&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031352134&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0031352134

SP - 70

EP - 73

BT - IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Proceedings

PB - IEEE

T2 - Proceedings of the 1997 19th Annual GaAs IC Symposium

Y2 - 12 October 1997 through 15 October 1997

ER -

0.1-μm double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs

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