0.1-μm p+-GaAs gate HJFET's fabricated using two-step dry-etching and selective MOMBE growth techniques

Shigeki Wada, Naoki Furuhata, Masatoshi Tokushima, Muneo Fukaishi, Hikaru Hida, Tadashi Maeda

Research output: Research - peer-reviewArticle

  • 1 Citations

Abstract

This paper reports the first successful fabrication of high-performance, 0.1-μm p+-gate pseudomorphic heterojunction-FET's (HJFET's). By introducing the two-step dry-etching technique which compensates for the poor dry-etching resistance of PMMA, 0.1-jum or less gate-openings with a high aspect-ratio of 3.5 in SiO2 film are achieved. In addition, by using the gate-electrode filling technique with selective MOMBE p+-GaAs growth, 0.1-jum voidless p+-GaAs gate electrodes with a high aspect-ratio are achieved for the first time. The fabrication technology leads to a reduction of external gate fringing capacitance (Cf ext) in a T-shaped gate-structure and an improvement in gate turn-on voltage. The fabricated 0.1-jum, T-shaped, p+-gate n-Al0.2Gao.sAs/In0 25Ga0.7sAs HJFET exhibits a high gate turn-on voltage (V>) of about 0.9 V, and a good gmmax of 435 mS/mm. Also, an excellent microwave performance of fT = 121 GHz and /max = 144 GHz is achieved due to the Cf ext reduction. The technology and device show great promise for future high-speed applications, such as in power devices, MMIC's, and digital IC's.

LanguageEnglish
Pages1183-1189
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume45
Issue number6
DOIs
StatePublished - 1998
Externally publishedYes

Fingerprint

Dry etching
Field effect transistors
Heterojunctions
Aspect ratio
Fabrication
Electrodes
Electric potential
gallium arsenide
heterojunctions
field effect transistors
etching
Monolithic microwave integrated circuits
Polymethyl Methacrylate
Capacitance
Microwaves
high aspect ratio
fabrication
electrodes
electric potential
gates (openings)

Keywords

  • Crystals
  • Etching
  • Jfet's
  • Modfet's
  • Plasma materials
  • Processing application

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

Cite this

0.1-μm p+-GaAs gate HJFET's fabricated using two-step dry-etching and selective MOMBE growth techniques. / Wada, Shigeki; Furuhata, Naoki; Tokushima, Masatoshi; Fukaishi, Muneo; Hida, Hikaru; Maeda, Tadashi.

In: IEEE Transactions on Electron Devices, Vol. 45, No. 6, 1998, p. 1183-1189.

Research output: Research - peer-reviewArticle

Wada, Shigeki ; Furuhata, Naoki ; Tokushima, Masatoshi ; Fukaishi, Muneo ; Hida, Hikaru ; Maeda, Tadashi. / 0.1-μm p+-GaAs gate HJFET's fabricated using two-step dry-etching and selective MOMBE growth techniques. In: IEEE Transactions on Electron Devices. 1998 ; Vol. 45, No. 6. pp. 1183-1189
@article{d67beb60a1484ca8909022cb3bad8ab8,
title = "0.1-μm p+-GaAs gate HJFET's fabricated using two-step dry-etching and selective MOMBE growth techniques",
abstract = "This paper reports the first successful fabrication of high-performance, 0.1-μm p+-gate pseudomorphic heterojunction-FET's (HJFET's). By introducing the two-step dry-etching technique which compensates for the poor dry-etching resistance of PMMA, 0.1-jum or less gate-openings with a high aspect-ratio of 3.5 in SiO2 film are achieved. In addition, by using the gate-electrode filling technique with selective MOMBE p+-GaAs growth, 0.1-jum voidless p+-GaAs gate electrodes with a high aspect-ratio are achieved for the first time. The fabrication technology leads to a reduction of external gate fringing capacitance (Cf ext) in a T-shaped gate-structure and an improvement in gate turn-on voltage. The fabricated 0.1-jum, T-shaped, p+-gate n-Al0.2Gao.sAs/In0 25Ga0.7sAs HJFET exhibits a high gate turn-on voltage (V>) of about 0.9 V, and a good gmmax of 435 mS/mm. Also, an excellent microwave performance of fT = 121 GHz and /max = 144 GHz is achieved due to the Cf ext reduction. The technology and device show great promise for future high-speed applications, such as in power devices, MMIC's, and digital IC's.",
keywords = "Crystals, Etching, Jfet's, Modfet's, Plasma materials, Processing application",
author = "Shigeki Wada and Naoki Furuhata and Masatoshi Tokushima and Muneo Fukaishi and Hikaru Hida and Tadashi Maeda",
year = "1998",
doi = "10.1109/16.678505",
volume = "45",
pages = "1183--1189",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "6",

}

TY - JOUR

T1 - 0.1-μm p+-GaAs gate HJFET's fabricated using two-step dry-etching and selective MOMBE growth techniques

AU - Wada,Shigeki

AU - Furuhata,Naoki

AU - Tokushima,Masatoshi

AU - Fukaishi,Muneo

AU - Hida,Hikaru

AU - Maeda,Tadashi

PY - 1998

Y1 - 1998

N2 - This paper reports the first successful fabrication of high-performance, 0.1-μm p+-gate pseudomorphic heterojunction-FET's (HJFET's). By introducing the two-step dry-etching technique which compensates for the poor dry-etching resistance of PMMA, 0.1-jum or less gate-openings with a high aspect-ratio of 3.5 in SiO2 film are achieved. In addition, by using the gate-electrode filling technique with selective MOMBE p+-GaAs growth, 0.1-jum voidless p+-GaAs gate electrodes with a high aspect-ratio are achieved for the first time. The fabrication technology leads to a reduction of external gate fringing capacitance (Cf ext) in a T-shaped gate-structure and an improvement in gate turn-on voltage. The fabricated 0.1-jum, T-shaped, p+-gate n-Al0.2Gao.sAs/In0 25Ga0.7sAs HJFET exhibits a high gate turn-on voltage (V>) of about 0.9 V, and a good gmmax of 435 mS/mm. Also, an excellent microwave performance of fT = 121 GHz and /max = 144 GHz is achieved due to the Cf ext reduction. The technology and device show great promise for future high-speed applications, such as in power devices, MMIC's, and digital IC's.

AB - This paper reports the first successful fabrication of high-performance, 0.1-μm p+-gate pseudomorphic heterojunction-FET's (HJFET's). By introducing the two-step dry-etching technique which compensates for the poor dry-etching resistance of PMMA, 0.1-jum or less gate-openings with a high aspect-ratio of 3.5 in SiO2 film are achieved. In addition, by using the gate-electrode filling technique with selective MOMBE p+-GaAs growth, 0.1-jum voidless p+-GaAs gate electrodes with a high aspect-ratio are achieved for the first time. The fabrication technology leads to a reduction of external gate fringing capacitance (Cf ext) in a T-shaped gate-structure and an improvement in gate turn-on voltage. The fabricated 0.1-jum, T-shaped, p+-gate n-Al0.2Gao.sAs/In0 25Ga0.7sAs HJFET exhibits a high gate turn-on voltage (V>) of about 0.9 V, and a good gmmax of 435 mS/mm. Also, an excellent microwave performance of fT = 121 GHz and /max = 144 GHz is achieved due to the Cf ext reduction. The technology and device show great promise for future high-speed applications, such as in power devices, MMIC's, and digital IC's.

KW - Crystals

KW - Etching

KW - Jfet's

KW - Modfet's

KW - Plasma materials

KW - Processing application

UR - http://www.scopus.com/inward/record.url?scp=0032094878&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032094878&partnerID=8YFLogxK

U2 - 10.1109/16.678505

DO - 10.1109/16.678505

M3 - Article

VL - 45

SP - 1183

EP - 1189

JO - IEEE Transactions on Electron Devices

T2 - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 6

ER -