0.1-μm self-aligned-gate GaAs MESFET with multilayer interconnection structure for ultra-high-speed ICs

Masami Tokumitsu, Makoto Hirano, Taiichi Otsuji, Satoshi Yamaguchi, Kimiyoshi Yamasaki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 13 Citations

Abstract

We have developed the technologies to fabricate about 0.1-μm-gate-length GaAs MESFETs with a multilayer interconnection structure. We fabricated excellent high-frequency performance of a 0.06-μm-gate-length MESFET having current-gain cutoff frequency (f T) of 168 GHz. Using 0.13-μm-gate-length MESFETs, we also fabricated an ultra-high-speed decision circuit operating up to 32 Gbit/s.

LanguageEnglish
Title of host publicationTechnical Digest - International Electron Devices Meeting
Editors Anon
PublisherIEEE
Pages211-214
Number of pages4
StatePublished - 1996
Externally publishedYes
EventProceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 1996 Dec 81996 Dec 11

Other

OtherProceedings of the 1996 IEEE International Electron Devices Meeting
CitySan Francisco, CA, USA
Period96/12/896/12/11

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Cutoff frequency
Multilayers
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Tokumitsu, M., Hirano, M., Otsuji, T., Yamaguchi, S., & Yamasaki, K. (1996). 0.1-μm self-aligned-gate GaAs MESFET with multilayer interconnection structure for ultra-high-speed ICs. In Anon (Ed.), Technical Digest - International Electron Devices Meeting (pp. 211-214). IEEE.

0.1-μm self-aligned-gate GaAs MESFET with multilayer interconnection structure for ultra-high-speed ICs. / Tokumitsu, Masami; Hirano, Makoto; Otsuji, Taiichi; Yamaguchi, Satoshi; Yamasaki, Kimiyoshi.

Technical Digest - International Electron Devices Meeting. ed. / Anon. IEEE, 1996. p. 211-214.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tokumitsu, M, Hirano, M, Otsuji, T, Yamaguchi, S & Yamasaki, K 1996, 0.1-μm self-aligned-gate GaAs MESFET with multilayer interconnection structure for ultra-high-speed ICs. in Anon (ed.), Technical Digest - International Electron Devices Meeting. IEEE, pp. 211-214, Proceedings of the 1996 IEEE International Electron Devices Meeting, San Francisco, CA, USA, 96/12/8.
Tokumitsu M, Hirano M, Otsuji T, Yamaguchi S, Yamasaki K. 0.1-μm self-aligned-gate GaAs MESFET with multilayer interconnection structure for ultra-high-speed ICs. In Anon, editor, Technical Digest - International Electron Devices Meeting. IEEE. 1996. p. 211-214.
Tokumitsu, Masami ; Hirano, Makoto ; Otsuji, Taiichi ; Yamaguchi, Satoshi ; Yamasaki, Kimiyoshi. / 0.1-μm self-aligned-gate GaAs MESFET with multilayer interconnection structure for ultra-high-speed ICs. Technical Digest - International Electron Devices Meeting. editor / Anon. IEEE, 1996. pp. 211-214
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