0.6V supply voltage 0.25 μm E/D-HJFET(IS3T) LSI technology for low power consumption and high speed LSIs

H. Hida, M. Tokushima, Tadashi Maeda, M. Ishikawa, M. Fukaishi, K. Numata, Y. Ohno

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

A new technology of fabricating 0.25 μm gate E/D-heterojunction FET LSIs is developed as a step towards the development of ultra low supply voltage LSIs. This technology, which is based upon all dry-process techniques, includes the formation of a 0.25 μm gate opening through the use of optical lithography and inner SiO2 sidewalls. The fmax and the gmmax for a Y-shaped gate E-HJFET are 108 GHz and 520 mS/mm, respectively. Excellent performances are obtained with DCFL ring oscillators using n-AlGaAs/i-InGaAs pseudomorphic E/D-HJFETs. These include 18 ps/G unloaded delay and 109 ps/G loaded delay (FI=FO=3, L=1mm) with 0.15 mW/G at a low supply voltage of 0.6 V, where inverters have a sufficient noise margin of more than 180 mV. Also, 10 Gbps error-free operation of a selector switch is demonstrated with 9.4 mW at 0.6 V.

Original languageEnglish
Title of host publicationTechnical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)
Editors Anon
PublisherPubl by IEEE
Pages197-200
Number of pages4
ISBN (Print)0780313933
Publication statusPublished - 1993
Externally publishedYes
EventProceedings of the 15th Annual IEEE GaAs IC Symposium - San Jose, CA, USA
Duration: 1993 Oct 101993 Oct 13

Other

OtherProceedings of the 15th Annual IEEE GaAs IC Symposium
CitySan Jose, CA, USA
Period93/10/1093/10/13

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Hida, H., Tokushima, M., Maeda, T., Ishikawa, M., Fukaishi, M., Numata, K., & Ohno, Y. (1993). 0.6V supply voltage 0.25 μm E/D-HJFET(IS3T) LSI technology for low power consumption and high speed LSIs. In Anon (Ed.), Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit) (pp. 197-200). Publ by IEEE.