110Gb/s multiplexing and demultiplexing ICs

Yasuyuki Suzuki; Yasushi Amamiya; Zin Yamazaki; Shigeki Wada; Hiroaki Uchida; Chiharu Kurioka; Shinichi Tanaka; Hikaru Hida

110Gb/s multiplexing and demultiplexing ICs

Yasuyuki Suzuki, Yasushi Amamiya, Zin Yamazaki, Shigeki Wada, Hiroaki Uchida, Chiharu Kurioka, Shinichi Tanaka, Hikaru Hida

Research output: Contribution to journal › Conference article › peer-review

4 Citations (Scopus)

Abstract

A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.

Original language	English
Pages (from-to)	182-183+518
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	47
Publication status	Published - 2003 Dec 1
Externally published	Yes
Event	Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement - San Francisco, CA., United States Duration: 2003 Feb 15 → 2003 Feb 19

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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abstract = "A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.",

author = "Yasuyuki Suzuki and Yasushi Amamiya and Zin Yamazaki and Shigeki Wada and Hiroaki Uchida and Chiharu Kurioka and Shinichi Tanaka and Hikaru Hida",

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journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

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T1 - 110Gb/s multiplexing and demultiplexing ICs

AU - Suzuki, Yasuyuki

AU - Amamiya, Yasushi

AU - Yamazaki, Zin

AU - Wada, Shigeki

AU - Uchida, Hiroaki

AU - Kurioka, Chiharu

AU - Tanaka, Shinichi

AU - Hida, Hikaru

PY - 2003/12/1

Y1 - 2003/12/1

N2 - A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.

AB - A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.

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M3 - Conference article

AN - SCOPUS:2442703020

SN - 0193-6530

VL - 47

SP - 182-183+518

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement

Y2 - 15 February 2003 through 19 February 2003

ER -

110Gb/s multiplexing and demultiplexing ICs

Abstract

ASJC Scopus subject areas

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