110Gb/s multiplexing and demultiplexing ICs

Yasuyuki Suzuki, Yasushi Amamiya, Zin Yamazaki, Shigeki Wada, Hiroaki Uchida, Chiharu Kurioka, Shinichi Tanaka, Hikaru Hida

Research output: Contribution to journalConference articlepeer-review

4 Citations (Scopus)


A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.

Original languageEnglish
Pages (from-to)182-183+518
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 2003 Dec 1
Externally publishedYes
EventDigest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement - San Francisco, CA., United States
Duration: 2003 Feb 152003 Feb 19

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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