110Gb/s multiplexing and demultiplexing ICs

Yasuyuki Suzuki, Yasushi Amamiya, Zin Yamazaki, Shigeki Wada, Hiroaki Uchida, Chiharu Kurioka, Shinichi Tanaka, Hikaru Hida

Research output: ResearchConference contribution

  • 4 Citations

Abstract

A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.

LanguageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
EditorsL.C. Fujino, M. Amiri, A. Grabel, D. Jaeger, K.C. Smith
Pages182-183+518
Volume47
StatePublished - 2003
Externally publishedYes
EventDigest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement - San Francisco, CA., United States
Duration: 2003 Feb 152003 Feb 19

Other

OtherDigest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement
CountryUnited States
CitySan Francisco, CA.
Period03/2/1503/2/19

Fingerprint

Demultiplexing
Flip flop circuits
Multiplexing
Strip telecommunication lines
Heterojunction bipolar transistors

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Suzuki, Y., Amamiya, Y., Yamazaki, Z., Wada, S., Uchida, H., Kurioka, C., ... Hida, H. (2003). 110Gb/s multiplexing and demultiplexing ICs. In L. C. Fujino, M. Amiri, A. Grabel, D. Jaeger, & K. C. Smith (Eds.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 47, pp. 182-183+518)

110Gb/s multiplexing and demultiplexing ICs. / Suzuki, Yasuyuki; Amamiya, Yasushi; Yamazaki, Zin; Wada, Shigeki; Uchida, Hiroaki; Kurioka, Chiharu; Tanaka, Shinichi; Hida, Hikaru.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. ed. / L.C. Fujino; M. Amiri; A. Grabel; D. Jaeger; K.C. Smith. Vol. 47 2003. p. 182-183+518.

Research output: ResearchConference contribution

Suzuki, Y, Amamiya, Y, Yamazaki, Z, Wada, S, Uchida, H, Kurioka, C, Tanaka, S & Hida, H 2003, 110Gb/s multiplexing and demultiplexing ICs. in LC Fujino, M Amiri, A Grabel, D Jaeger & KC Smith (eds), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 47, pp. 182-183+518, Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement, San Francisco, CA., United States, 03/2/15.
Suzuki Y, Amamiya Y, Yamazaki Z, Wada S, Uchida H, Kurioka C et al. 110Gb/s multiplexing and demultiplexing ICs. In Fujino LC, Amiri M, Grabel A, Jaeger D, Smith KC, editors, Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 47. 2003. p. 182-183+518.
Suzuki, Yasuyuki ; Amamiya, Yasushi ; Yamazaki, Zin ; Wada, Shigeki ; Uchida, Hiroaki ; Kurioka, Chiharu ; Tanaka, Shinichi ; Hida, Hikaru. / 110Gb/s multiplexing and demultiplexing ICs. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. editor / L.C. Fujino ; M. Amiri ; A. Grabel ; D. Jaeger ; K.C. Smith. Vol. 47 2003. pp. 182-183+518
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