110Gb/s multiplexing and demultiplexing ICs

Yasuyuki Suzuki, Yasushi Amamiya, Zin Yamazaki, Shigeki Wada, Hiroaki Uchida, Chiharu Kurioka, Shinichi Tanaka, Hikaru Hida

Research output: Contribution to journalConference article

4 Citations (Scopus)

Abstract

A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.

Original languageEnglish
Pages (from-to)182-183+518
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume47
Publication statusPublished - 2003 Dec 1
EventDigest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement - San Francisco, CA., United States
Duration: 2003 Feb 152003 Feb 19

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of '110Gb/s multiplexing and demultiplexing ICs'. Together they form a unique fingerprint.

  • Cite this

    Suzuki, Y., Amamiya, Y., Yamazaki, Z., Wada, S., Uchida, H., Kurioka, C., Tanaka, S., & Hida, H. (2003). 110Gb/s multiplexing and demultiplexing ICs. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 47, 182-183+518.