120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs

Yasuyuki Suzuki, Zin Yamazaki, Yasushi Amamiya, Shigeki Wada, Hiroaki Uchida, Chiharu Kurioka, Shinichi Tanaka, Hikaru Hida

Research output: Contribution to journalArticle

  • 43 Citations

Abstract

InP HBT ICs capable of 120-Gb/s multiplexing and 110-Gb/s demultiplexing operation have been developed. They feature a direct-drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted microstrip lines. Their input sensitivity is less than 100 mVpp, and the output swing is more than 400 mV pp. To the best of our knowledge, this result is the highest data rate operation reported for electronic ICs. Moreover, error-free multiplexing and demultiplexing operation at 100 Gb/s was demonstrated.

LanguageEnglish
Pages2397-2402
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume39
Issue number12
DOIs
StatePublished - 2004 Dec
Externally publishedYes

Fingerprint

Demultiplexing
Flip flop circuits
Multiplexing
Microstrip lines
Heterojunction bipolar transistors

Keywords

  • Demultiplexing
  • Error-free operation
  • Flip-flop
  • Impedance matching
  • InP HBT
  • Multiplexing
  • Optical transmission system
  • Selector

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Suzuki, Y., Yamazaki, Z., Amamiya, Y., Wada, S., Uchida, H., Kurioka, C., ... Hida, H. (2004). 120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs. IEEE Journal of Solid-State Circuits, 39(12), 2397-2402. DOI: 10.1109/JSSC.2004.835647

120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs. / Suzuki, Yasuyuki; Yamazaki, Zin; Amamiya, Yasushi; Wada, Shigeki; Uchida, Hiroaki; Kurioka, Chiharu; Tanaka, Shinichi; Hida, Hikaru.

In: IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, 12.2004, p. 2397-2402.

Research output: Contribution to journalArticle

Suzuki, Y, Yamazaki, Z, Amamiya, Y, Wada, S, Uchida, H, Kurioka, C, Tanaka, S & Hida, H 2004, '120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs' IEEE Journal of Solid-State Circuits, vol 39, no. 12, pp. 2397-2402. DOI: 10.1109/JSSC.2004.835647
Suzuki Y, Yamazaki Z, Amamiya Y, Wada S, Uchida H, Kurioka C et al. 120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs. IEEE Journal of Solid-State Circuits. 2004 Dec;39(12):2397-2402. Available from, DOI: 10.1109/JSSC.2004.835647
Suzuki, Yasuyuki ; Yamazaki, Zin ; Amamiya, Yasushi ; Wada, Shigeki ; Uchida, Hiroaki ; Kurioka, Chiharu ; Tanaka, Shinichi ; Hida, Hikaru. / 120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs. In: IEEE Journal of Solid-State Circuits. 2004 ; Vol. 39, No. 12. pp. 2397-2402
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