Abstract
In order to discuss stress-induced voiding (SIV) of Cu damascene interconnect structures in ultra-large-scale integrated circuits (ULSIs), 3-D elastic-plastic finite element analysis (FEA) was carried out based on stress-temperature behavior of constituent thin films measured by a wafer curvature method. Two types of Cu interconnect geometries with either p-SiN cap/p-SiON etch-stop layers on p-SiCN: H cap/p-SiC: H etch-stop layers were analyzed. The effect of the Cu line width was also investigated. It was found from the FEA results that, regardless of the geometry, the hydrostatic tensile stress of Cu in the structure with p-SiCN: H/p-SiC: H layers was generally lower than that with p-SiN/p-SiON layers. It was also expected that, for the structure with p-SiN/p-SiON layers, SIV is most likely to occur near the via center while for the structure with p-SiCN: H/p-SiC: H layers, it is most likely to occur near the via bottom. In the structure with p-SiCN: H/p-SiC: H layers, it was considered that a larger line width is susceptible to voiding in the via due to a high hydrostatic stress gradient in the via and a high magnitude of equivalent plastic strain in the line.
| Original language | English |
|---|---|
| Pages (from-to) | 964-971 |
| Number of pages | 8 |
| Journal | Nippon Kikai Gakkai Ronbunshu, A Hen/Transactions of the Japan Society of Mechanical Engineers, Part A |
| Volume | 69 |
| Issue number | 6 |
| Publication status | Published - 2003 Jun |
| Externally published | Yes |
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Keywords
- Cu damascene interconnect
- Elastic-plastic analysis
- Finite element method
- Intrinsic stress
- LSI
- Residual stress
- Stress-induced voiding
- Thermal stress
- Thin film
ASJC Scopus subject areas
- Mechanical Engineering
Cite this
3-Dimensional elastic-plastic finite element analysis of stress-induced voiding in Cu damascene interconnects of ultra-large-scale integrated circuits. / Saitoh, Takehiro; Kawano, Masaya; Ueno, Kazuyoshi.
In: Nippon Kikai Gakkai Ronbunshu, A Hen/Transactions of the Japan Society of Mechanical Engineers, Part A, Vol. 69, No. 6, 06.2003, p. 964-971.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - 3-Dimensional elastic-plastic finite element analysis of stress-induced voiding in Cu damascene interconnects of ultra-large-scale integrated circuits
AU - Saitoh, Takehiro
AU - Kawano, Masaya
AU - Ueno, Kazuyoshi
PY - 2003/6
Y1 - 2003/6
N2 - In order to discuss stress-induced voiding (SIV) of Cu damascene interconnect structures in ultra-large-scale integrated circuits (ULSIs), 3-D elastic-plastic finite element analysis (FEA) was carried out based on stress-temperature behavior of constituent thin films measured by a wafer curvature method. Two types of Cu interconnect geometries with either p-SiN cap/p-SiON etch-stop layers on p-SiCN: H cap/p-SiC: H etch-stop layers were analyzed. The effect of the Cu line width was also investigated. It was found from the FEA results that, regardless of the geometry, the hydrostatic tensile stress of Cu in the structure with p-SiCN: H/p-SiC: H layers was generally lower than that with p-SiN/p-SiON layers. It was also expected that, for the structure with p-SiN/p-SiON layers, SIV is most likely to occur near the via center while for the structure with p-SiCN: H/p-SiC: H layers, it is most likely to occur near the via bottom. In the structure with p-SiCN: H/p-SiC: H layers, it was considered that a larger line width is susceptible to voiding in the via due to a high hydrostatic stress gradient in the via and a high magnitude of equivalent plastic strain in the line.
AB - In order to discuss stress-induced voiding (SIV) of Cu damascene interconnect structures in ultra-large-scale integrated circuits (ULSIs), 3-D elastic-plastic finite element analysis (FEA) was carried out based on stress-temperature behavior of constituent thin films measured by a wafer curvature method. Two types of Cu interconnect geometries with either p-SiN cap/p-SiON etch-stop layers on p-SiCN: H cap/p-SiC: H etch-stop layers were analyzed. The effect of the Cu line width was also investigated. It was found from the FEA results that, regardless of the geometry, the hydrostatic tensile stress of Cu in the structure with p-SiCN: H/p-SiC: H layers was generally lower than that with p-SiN/p-SiON layers. It was also expected that, for the structure with p-SiN/p-SiON layers, SIV is most likely to occur near the via center while for the structure with p-SiCN: H/p-SiC: H layers, it is most likely to occur near the via bottom. In the structure with p-SiCN: H/p-SiC: H layers, it was considered that a larger line width is susceptible to voiding in the via due to a high hydrostatic stress gradient in the via and a high magnitude of equivalent plastic strain in the line.
KW - Cu damascene interconnect
KW - Elastic-plastic analysis
KW - Finite element method
KW - Intrinsic stress
KW - LSI
KW - Residual stress
KW - Stress-induced voiding
KW - Thermal stress
KW - Thin film
UR - http://www.scopus.com/inward/record.url?scp=0042890514&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0042890514&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0042890514
VL - 69
SP - 964
EP - 971
JO - Nihon Kikai Gakkai Ronbunshu, A Hen/Transactions of the Japan Society of Mechanical Engineers, Part A
JF - Nihon Kikai Gakkai Ronbunshu, A Hen/Transactions of the Japan Society of Mechanical Engineers, Part A
SN - 0387-5008
IS - 6
ER -