4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOS

Masahiro Sasaki, Makoto Ikeda, Kunihiro Asada

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A 4-Gb/s, low-power, 231-1 output length, Pseudo Random Binary Sequence (PRBS) generator with a wave-pipeline technique is presented. A thirty-one stages Linear Feedback Shift Register (LFSR), whose feedback taps are connected to the first stage through EXOR, is adopted. In this LFSR, each stage consists of D-FF employing a True Single Phase Clock (TSPC) type to increase the operating frequency. In the conventional design, to obtain correct output from feedback loop under high-speed operation, the propagation delay of the critical path containing D-FF and EXOR must be less than one shifting clock period. The proposed wave-pipeline technique bypasses the portion of feedback loop, and thereby relaxes the restriction of this path up to two shifting clock periods. Applying this method, the delay of critical path can be reduced to D-FF's one. As a result of this improvement, the proposed generator operates at 48% higher frequency than the conventional one. Besides the performance enhancement, this generator occupies small area and consumes low power because of employing standard CMOS logic. Therefore, the proposed circuit can be implemented in System on Chip (SoC) and perform an Accelerated Error Test as a part of Built-in Self Tester (BIST) for the serial link based on standard static CMOS logic. This circuit was simulated in a 0.18-μm 1P5M CMOS process. The total power dissipation at 4-Gb/s and 1.8-V supply voltage is 9.5mW and the active area is 0.004mm2.

Original languageEnglish
Title of host publicationProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Pages1007-1010
Number of pages4
DOIs
Publication statusPublished - 2006
Externally publishedYes
EventICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems - Nice
Duration: 2006 Dec 102006 Dec 13

Other

OtherICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
CityNice
Period06/12/1006/12/13

Fingerprint

Binary sequences
Pipelines
Feedback
Clocks
Shift registers
Networks (circuits)
Energy dissipation
Electric potential

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Sasaki, M., Ikeda, M., & Asada, K. (2006). 4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOS. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (pp. 1007-1010). [4263539] https://doi.org/10.1109/ICECS.2006.379961

4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOS. / Sasaki, Masahiro; Ikeda, Makoto; Asada, Kunihiro.

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. 2006. p. 1007-1010 4263539.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sasaki, M, Ikeda, M & Asada, K 2006, 4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOS. in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems., 4263539, pp. 1007-1010, ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems, Nice, 06/12/10. https://doi.org/10.1109/ICECS.2006.379961
Sasaki M, Ikeda M, Asada K. 4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOS. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. 2006. p. 1007-1010. 4263539 https://doi.org/10.1109/ICECS.2006.379961
Sasaki, Masahiro ; Ikeda, Makoto ; Asada, Kunihiro. / 4-Gb/s low-power PRBS Generator with wave-pipeline technique in 0.18-μm CMOS. Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. 2006. pp. 1007-1010
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