60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Masafumi Takahashi; Mototsugu Hamada; Tsuyoshi Nishikawa; Hideho Arakida; Yoshiaki Tsuboi; Tetsuya Fujita; Fumihiro Hatori; Shinji Mita; Kojirou Suzuki; Akihiko Chiba; Toshihiro Terazawa; Fumihiko Sano; Yoshinori Watanabe; Hiroshi Momose; Kimiyoshi Usami

60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Yoshiaki Tsuboi, Tetsuya Fujita, Fumihiro Hatori, Shinji Mita, Kojirou Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Hiroshi Momose, Kimiyoshi Usami

Research output: Contribution to journal › Conference article › peer-review

13 Citations (Scopus)

Abstract

The Motion Picture Experts Group (MPEG)4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power dissipation of a conventional CMOS design. Measured power dissipation is presented. 70% power reduction is achieved by low-power techniques at circuit and architectural levels. Another way to reduce power dissipation is to reduce supply voltage without lower threshold voltage of those circuit clusters where the speed required is much lower than in critical paths. This clustered voltage scaling technique (CVS) reduces power dissipation without degrading chip operating frequency.

Original language	English
Pages (from-to)	36-37
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication status	Published - 1998
Externally published	Yes
Event	Proceedings of the 1998 IEEE 45th International Solid-State Circuits Conference, ISSCC - San Francisco, CA, USA Duration: 1998 Feb 5 → 1998 Feb 7

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Tsuboi, Y., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Momose, H., & Usami, K. (1998). 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 36-37.

60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. / Takahashi, Masafumi; Hamada, Mototsugu; Nishikawa, Tsuyoshi; Arakida, Hideho; Tsuboi, Yoshiaki; Fujita, Tetsuya; Hatori, Fumihiro; Mita, Shinji; Suzuki, Kojirou; Chiba, Akihiko; Terazawa, Toshihiro; Sano, Fumihiko; Watanabe, Yoshinori; Momose, Hiroshi; Usami, Kimiyoshi.

In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 1998, p. 36-37.

Research output: Contribution to journal › Conference article › peer-review

Takahashi, Masafumi ; Hamada, Mototsugu ; Nishikawa, Tsuyoshi ; Arakida, Hideho ; Tsuboi, Yoshiaki ; Fujita, Tetsuya ; Hatori, Fumihiro ; Mita, Shinji ; Suzuki, Kojirou ; Chiba, Akihiko ; Terazawa, Toshihiro ; Sano, Fumihiko ; Watanabe, Yoshinori ; Momose, Hiroshi ; Usami, Kimiyoshi. / 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 1998 ; pp. 36-37.

@article{c7a2e51caa63430fbba9d85dadd8ce4e,

title = "60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme",

abstract = "The Motion Picture Experts Group (MPEG)4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power dissipation of a conventional CMOS design. Measured power dissipation is presented. 70% power reduction is achieved by low-power techniques at circuit and architectural levels. Another way to reduce power dissipation is to reduce supply voltage without lower threshold voltage of those circuit clusters where the speed required is much lower than in critical paths. This clustered voltage scaling technique (CVS) reduces power dissipation without degrading chip operating frequency.",

author = "Masafumi Takahashi and Mototsugu Hamada and Tsuyoshi Nishikawa and Hideho Arakida and Yoshiaki Tsuboi and Tetsuya Fujita and Fumihiro Hatori and Shinji Mita and Kojirou Suzuki and Akihiko Chiba and Toshihiro Terazawa and Fumihiko Sano and Yoshinori Watanabe and Hiroshi Momose and Kimiyoshi Usami",

year = "1998",

language = "English",

pages = "36--37",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1998 IEEE 45th International Solid-State Circuits Conference, ISSCC ; Conference date: 05-02-1998 Through 07-02-1998",

}

TY - JOUR

T1 - 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

AU - Takahashi, Masafumi

AU - Hamada, Mototsugu

AU - Nishikawa, Tsuyoshi

AU - Arakida, Hideho

AU - Tsuboi, Yoshiaki

AU - Fujita, Tetsuya

AU - Hatori, Fumihiro

AU - Mita, Shinji

AU - Suzuki, Kojirou

AU - Chiba, Akihiko

AU - Terazawa, Toshihiro

AU - Sano, Fumihiko

AU - Watanabe, Yoshinori

AU - Momose, Hiroshi

AU - Usami, Kimiyoshi

PY - 1998

Y1 - 1998

N2 - The Motion Picture Experts Group (MPEG)4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power dissipation of a conventional CMOS design. Measured power dissipation is presented. 70% power reduction is achieved by low-power techniques at circuit and architectural levels. Another way to reduce power dissipation is to reduce supply voltage without lower threshold voltage of those circuit clusters where the speed required is much lower than in critical paths. This clustered voltage scaling technique (CVS) reduces power dissipation without degrading chip operating frequency.

AB - The Motion Picture Experts Group (MPEG)4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power dissipation of a conventional CMOS design. Measured power dissipation is presented. 70% power reduction is achieved by low-power techniques at circuit and architectural levels. Another way to reduce power dissipation is to reduce supply voltage without lower threshold voltage of those circuit clusters where the speed required is much lower than in critical paths. This clustered voltage scaling technique (CVS) reduces power dissipation without degrading chip operating frequency.

UR - http://www.scopus.com/inward/record.url?scp=0031652001&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031652001&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0031652001

SP - 36

EP - 37

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SN - 0193-6530

T2 - Proceedings of the 1998 IEEE 45th International Solid-State Circuits Conference, ISSCC

Y2 - 5 February 1998 through 7 February 1998

ER -

60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Abstract

ASJC Scopus subject areas

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