7-mask CMOS process with selective oxide deposition

Tadahiko Horiuchi, Kouji Kanba, Tetsuya Homma, Yukinobu Muro, Koichiro Okumura

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

This paper describes a new 7-mask CMOS process using liquid phase oxide deposition which has selectivity against photoresist. The process modules for self-aligned well and one mask LDD formation are developed. The features of the process are 1) short TAT: 7 masks to first metallization, 2) self-aligned twin retrograde wells with 40% reduction of the P+-n+ spacing compared to conventional wells, and 3) optimal LDD design using different sidewall spacer width for n- and p-channel MOSFET's giving a 10% larger on-current for p-channel MOSFET's compared to a conventional process.

Original languageEnglish
Pages (from-to)1455-1460
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume40
Issue number8
DOIs
Publication statusPublished - 1993 Aug
Externally publishedYes

Fingerprint

Oxides
Masks
CMOS
masks
oxides
field effect transistors
Photoresists
Metallizing
photoresists
spacers
liquid phases
modules
selectivity
spacing
Liquids
Optimal design

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

Cite this

7-mask CMOS process with selective oxide deposition. / Horiuchi, Tadahiko; Kanba, Kouji; Homma, Tetsuya; Muro, Yukinobu; Okumura, Koichiro.

In: IEEE Transactions on Electron Devices, Vol. 40, No. 8, 08.1993, p. 1455-1460.

Research output: Contribution to journalArticle

Horiuchi, Tadahiko ; Kanba, Kouji ; Homma, Tetsuya ; Muro, Yukinobu ; Okumura, Koichiro. / 7-mask CMOS process with selective oxide deposition. In: IEEE Transactions on Electron Devices. 1993 ; Vol. 40, No. 8. pp. 1455-1460.
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