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  • Kimiyoshi Usami
2017

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Yoshida, Y. & Usami, K., 2017 Jun 29, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 43-46 4 p. 7962596

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2019

Single Supply Level Shifter Circuit using body-bias

Takeyoshi, Y. & Usami, K., 2019 Jun, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 8793384. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2017

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Kudo, M. & Usami, K., 2017 Oct 10, NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium. Institute of Electrical and Electronics Engineers Inc., 8064472. (NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2020

Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

Usami, K., Akiba, S., Amano, H., Ikezoe, T., Hiraga, K., Suzuki, K. & Kanda, Y., 2020 Apr, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9097630. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2018

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yoshida, Y., Usami, K. & Amano, H., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 148-149 2 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2016

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Kamohara, S., Sugii, N., Ishibashi, K., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2016 May 25, 2014 IEEE Hot Chips 26 Symposium, HCS 2014. Institute of Electrical and Electronics Engineers Inc., 7478838

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2016 May 24, 2013 IEEE Hot Chips 25 Symposium, HCS 2013. Institute of Electrical and Electronics Engineers Inc., 7478328. (2013 IEEE Hot Chips 25 Symposium, HCS 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2017

Power Optimization Methodology for Ultralow Power Microcontroller with Silicon on Thin BOX MOSFET

Okuhara, H., Fujita, Y., Usami, K. & Amano, H., 2017 Apr, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 4, p. 1578-1582 5 p., 7802624.

Research output: Contribution to journalArticle

10 Citations (Scopus)

Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2017 Dec 13, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 8203473

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2018

Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2018 Mar 7, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-March. p. 1-3 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
2016

Multi-voltage variable pipeline routers with the same clock frequency for low-power network-on-chips systems

Ahmed, A. B., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2016 Aug 1, In : IEICE Transactions on Electronics. E99C, 8, p. 909-917 9 p.

Research output: Contribution to journalArticle

2 Citations (Scopus)
2019

A coarse grained-reconfigurable accelerator with energy efficient MTJ-based non-volatile flip-flops

Ikezoe, T., Amano, H., Akaike, J., Usami, K., Kudo, M., Hiraga, K., Shuto, Y. & Yagami, K., 2019 Feb 13, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018. Andrews, D., Feregrino, C., Cumplido, R. & Stroobandt, D. (eds.). Institute of Electrical and Electronics Engineers Inc., 8641712. (2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
2018

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami, K., Akaike, J., Akiba, S., Kudo, M., Amano, H., Ikezoe, T., Hiraga, K., Shuto, Y. & Yagami, K., 2018 Nov 15, Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., p. 91-98 8 p. 8537701. (Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)
2016

An operating system guided fine-grained power gating control based on runtime characteristics of applications

Koshiba, A., Sato, M., Usami, K., Amano, H., Sakamoto, R., Kondo, M., Nakamura, H. & Namiki, M., 2016 Aug 1, In : IEICE Transactions on Electronics. E99C, 8, p. 926-935 10 p.

Research output: Contribution to journalArticle

2018

Building block multi-chip systems using inductive coupling through chip interface

Amano, H., Kuroda, T., Nakamura, H., Usami, K., Kondo, M., Matsutani, H. & Namiki, M., 2018 May 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 152-154 3 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2019

Approximate Computing Technique Using Memoization and Simplified Multiplication

Ono, Y. & Usami, K., 2019 Jun, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 8793369. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2019 Jan 1, VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Revised and Extended Selected Papers. Monteiro, J., Elfadel, I. A. M., Sonza Reorda, M., Ugurdag, H. F., Maniatakos, M. & Reis, R. (eds.). Springer New York LLC, p. 1-21 21 p. (IFIP Advances in Information and Communication Technology; vol. 500).

Research output: Chapter in Book/Report/Conference proceedingConference contribution