A 0.25 μ m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs

H. Hida, M. Tokushima, M. Fukaishi, Tadashi Maeda, Y. Ohno

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

The first successful fabrication is reported for a high performance 0.25 μ m T-shaped gate pseudomorphic heterojunction FET without the conventional electron-beam lithography and wet etching technology, which often cause long turn-around times and poor reproducibility and controllability, resulting in big obstacles to producing GaAs LSIs. The novel device structure and fabrication process enables realizing very low power consumption GaAs VLSIs superior to even future Si LSIs, and have the following advantages. (i) 0.25 μ m gate formation by optical (stepper) lithography and anisotropic dry etching for SiO2 sidewalls, and smaller gate formation by an increase in sidewall thickness. (ii) Stable refractory metal gate electrode with low stress and high reliability. (iii) Low resistance T-shaped gate electrode of refractory and low resistivity multilayer metals. (iv) Small Rs and Rd due to ohmic electrodes self-aligned to T-shaped gate electrode, leading to small current saturation voltage Vdss, indispensable for low supply voltage controlled-LSIs. (v) Low damage dry etching of insulating films using low power magnetron ion etching. (vi) Formation of E/D-FETs with different VT using selective dry etching of GaAs to AlGaAs. (vii) High reproducibility and uniformity due to all dry etching technology.

Original languageEnglish
Title of host publication1992 International Technical Digest on Electron Devices Meeting, IEDM 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages982-984
Number of pages3
ISBN (Electronic)0780308174
DOIs
Publication statusPublished - 1992 Jan 1
Event1992 International Technical Digest on Electron Devices Meeting, IEDM 1992 - San Francisco, United States
Duration: 1992 Dec 131992 Dec 16

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume1992-December
ISSN (Print)0163-1918

Conference

Conference1992 International Technical Digest on Electron Devices Meeting, IEDM 1992
CountryUnited States
CitySan Francisco
Period92/12/1392/12/16

Fingerprint

Dry etching
large scale integration
Field effect transistors
low voltage
Heterojunctions
heterojunctions
field effect transistors
etching
Electrodes
Electric potential
electrodes
Fabrication
Anisotropic etching
Refractory metals
Turnaround time
Electron beam lithography
Wet etching
Photolithography
lithography
Controllability

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

Hida, H., Tokushima, M., Fukaishi, M., Maeda, T., & Ohno, Y. (1992). A 0.25 μ m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs. In 1992 International Technical Digest on Electron Devices Meeting, IEDM 1992 (pp. 982-984). [307591] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 1992-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.1992.307591

A 0.25 μ m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs. / Hida, H.; Tokushima, M.; Fukaishi, M.; Maeda, Tadashi; Ohno, Y.

1992 International Technical Digest on Electron Devices Meeting, IEDM 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 982-984 307591 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 1992-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hida, H, Tokushima, M, Fukaishi, M, Maeda, T & Ohno, Y 1992, A 0.25 μ m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs. in 1992 International Technical Digest on Electron Devices Meeting, IEDM 1992., 307591, Technical Digest - International Electron Devices Meeting, IEDM, vol. 1992-December, Institute of Electrical and Electronics Engineers Inc., pp. 982-984, 1992 International Technical Digest on Electron Devices Meeting, IEDM 1992, San Francisco, United States, 92/12/13. https://doi.org/10.1109/IEDM.1992.307591
Hida H, Tokushima M, Fukaishi M, Maeda T, Ohno Y. A 0.25 μ m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs. In 1992 International Technical Digest on Electron Devices Meeting, IEDM 1992. Institute of Electrical and Electronics Engineers Inc. 1992. p. 982-984. 307591. (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.1992.307591
Hida, H. ; Tokushima, M. ; Fukaishi, M. ; Maeda, Tadashi ; Ohno, Y. / A 0.25 μ m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs. 1992 International Technical Digest on Electron Devices Meeting, IEDM 1992. Institute of Electrical and Electronics Engineers Inc., 1992. pp. 982-984 (Technical Digest - International Electron Devices Meeting, IEDM).
@inproceedings{da9233cde0634ab0978a3520632c2589,
title = "A 0.25 μ m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs",
abstract = "The first successful fabrication is reported for a high performance 0.25 μ m T-shaped gate pseudomorphic heterojunction FET without the conventional electron-beam lithography and wet etching technology, which often cause long turn-around times and poor reproducibility and controllability, resulting in big obstacles to producing GaAs LSIs. The novel device structure and fabrication process enables realizing very low power consumption GaAs VLSIs superior to even future Si LSIs, and have the following advantages. (i) 0.25 μ m gate formation by optical (stepper) lithography and anisotropic dry etching for SiO2 sidewalls, and smaller gate formation by an increase in sidewall thickness. (ii) Stable refractory metal gate electrode with low stress and high reliability. (iii) Low resistance T-shaped gate electrode of refractory and low resistivity multilayer metals. (iv) Small Rs and Rd due to ohmic electrodes self-aligned to T-shaped gate electrode, leading to small current saturation voltage Vdss, indispensable for low supply voltage controlled-LSIs. (v) Low damage dry etching of insulating films using low power magnetron ion etching. (vi) Formation of E/D-FETs with different VT using selective dry etching of GaAs to AlGaAs. (vii) High reproducibility and uniformity due to all dry etching technology.",
author = "H. Hida and M. Tokushima and M. Fukaishi and Tadashi Maeda and Y. Ohno",
year = "1992",
month = "1",
day = "1",
doi = "10.1109/IEDM.1992.307591",
language = "English",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "982--984",
booktitle = "1992 International Technical Digest on Electron Devices Meeting, IEDM 1992",

}

TY - GEN

T1 - A 0.25 μ m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs

AU - Hida, H.

AU - Tokushima, M.

AU - Fukaishi, M.

AU - Maeda, Tadashi

AU - Ohno, Y.

PY - 1992/1/1

Y1 - 1992/1/1

N2 - The first successful fabrication is reported for a high performance 0.25 μ m T-shaped gate pseudomorphic heterojunction FET without the conventional electron-beam lithography and wet etching technology, which often cause long turn-around times and poor reproducibility and controllability, resulting in big obstacles to producing GaAs LSIs. The novel device structure and fabrication process enables realizing very low power consumption GaAs VLSIs superior to even future Si LSIs, and have the following advantages. (i) 0.25 μ m gate formation by optical (stepper) lithography and anisotropic dry etching for SiO2 sidewalls, and smaller gate formation by an increase in sidewall thickness. (ii) Stable refractory metal gate electrode with low stress and high reliability. (iii) Low resistance T-shaped gate electrode of refractory and low resistivity multilayer metals. (iv) Small Rs and Rd due to ohmic electrodes self-aligned to T-shaped gate electrode, leading to small current saturation voltage Vdss, indispensable for low supply voltage controlled-LSIs. (v) Low damage dry etching of insulating films using low power magnetron ion etching. (vi) Formation of E/D-FETs with different VT using selective dry etching of GaAs to AlGaAs. (vii) High reproducibility and uniformity due to all dry etching technology.

AB - The first successful fabrication is reported for a high performance 0.25 μ m T-shaped gate pseudomorphic heterojunction FET without the conventional electron-beam lithography and wet etching technology, which often cause long turn-around times and poor reproducibility and controllability, resulting in big obstacles to producing GaAs LSIs. The novel device structure and fabrication process enables realizing very low power consumption GaAs VLSIs superior to even future Si LSIs, and have the following advantages. (i) 0.25 μ m gate formation by optical (stepper) lithography and anisotropic dry etching for SiO2 sidewalls, and smaller gate formation by an increase in sidewall thickness. (ii) Stable refractory metal gate electrode with low stress and high reliability. (iii) Low resistance T-shaped gate electrode of refractory and low resistivity multilayer metals. (iv) Small Rs and Rd due to ohmic electrodes self-aligned to T-shaped gate electrode, leading to small current saturation voltage Vdss, indispensable for low supply voltage controlled-LSIs. (v) Low damage dry etching of insulating films using low power magnetron ion etching. (vi) Formation of E/D-FETs with different VT using selective dry etching of GaAs to AlGaAs. (vii) High reproducibility and uniformity due to all dry etching technology.

UR - http://www.scopus.com/inward/record.url?scp=85027147225&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85027147225&partnerID=8YFLogxK

U2 - 10.1109/IEDM.1992.307591

DO - 10.1109/IEDM.1992.307591

M3 - Conference contribution

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 982

EP - 984

BT - 1992 International Technical Digest on Electron Devices Meeting, IEDM 1992

PB - Institute of Electrical and Electronics Engineers Inc.

ER -