A 0.25 μ m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs

H. Hida, M. Tokushima, M. Fukaishi, Tadashi Maeda, Y. Ohno

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

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