A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps

Masahiro Fujii, Tadashi Maeda, Yasuo Ohno

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0. 25 μm n-AlGaAs/i-InGaAs HJFET process operates at up to lOGbps with power consumption as low as 19 mW at a supply voltage of 1. 3 V.

Original languageEnglish
Pages (from-to)512-516
Number of pages5
JournalIEICE Transactions on Electronics
VolumeE79-C
Issue number4
Publication statusPublished - 1996
Externally publishedYes

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Electric potential
Electric power utilization
Circuit simulation
Networks (circuits)

Keywords

  • D-FF
  • Gaas
  • Heterojunction fet
  • High speed
  • Logic swing
  • Low power
  • Low supply voltage
  • SCFL

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps. / Fujii, Masahiro; Maeda, Tadashi; Ohno, Yasuo.

In: IEICE Transactions on Electronics, Vol. E79-C, No. 4, 1996, p. 512-516.

Research output: Contribution to journalArticle

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