A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC

Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

All-digital phase-locked loops (ADPLLs) offer the advantages of eliminating the large on-chip passive filter and not suffering from poor low-supply-voltage operation with process scaling [1,2]. However, there is a challenge in achieving low power consumption at the same time as providing the low phase noise required in modern wireless systems like WiFi and WiMAX that have higher-order modulations. Recently, efforts improve phase noise have been accomplished by increasing the time resolution of the time-to-digital converter (TDC) using a gated ring-oscillator structure by using a multipath ring oscillator [3], 2-step structures based on a vernier delay line [4] or a time-amplifier [5,6]. However, these structures require large power consumption because they require many continuously operating high-speed delay-stages.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages470-471
Number of pages2
Volume53
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 IEEE International Solid-State Circuits Conference, ISSCC 2010 - San Francisco, CA, United States
Duration: 2010 Feb 72010 Feb 11

Other

Other2010 IEEE International Solid-State Circuits Conference, ISSCC 2010
CountryUnited States
CitySan Francisco, CA
Period10/2/710/2/11

Fingerprint

Frequency synthesizers
Phase noise
Electric power utilization
Passive filters
Electric delay lines
Phase locked loops
Modulation
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Tokairin, T., Okada, M., Kitsunezuka, M., Maeda, T., & Fukaishi, M. (2010). A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 53, pp. 470-471). [5433843] https://doi.org/10.1109/ISSCC.2010.5433843

A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. / Tokairin, Takashi; Okada, Mitsuji; Kitsunezuka, Masaki; Maeda, Tadashi; Fukaishi, Muneo.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 53 2010. p. 470-471 5433843.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tokairin, T, Okada, M, Kitsunezuka, M, Maeda, T & Fukaishi, M 2010, A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 53, 5433843, pp. 470-471, 2010 IEEE International Solid-State Circuits Conference, ISSCC 2010, San Francisco, CA, United States, 10/2/7. https://doi.org/10.1109/ISSCC.2010.5433843
Tokairin T, Okada M, Kitsunezuka M, Maeda T, Fukaishi M. A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 53. 2010. p. 470-471. 5433843 https://doi.org/10.1109/ISSCC.2010.5433843
Tokairin, Takashi ; Okada, Mitsuji ; Kitsunezuka, Masaki ; Maeda, Tadashi ; Fukaishi, Muneo. / A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 53 2010. pp. 470-471
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