A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS

N. Ozaki, Y. Yasuda, Y. Saito, D. Ikebuchi, M. Kimura, H. Amano, H. Nakamura, Kimiyoshi Usami, M. Namiki, M. Kondo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

CMA (Cool Mega-Array) is a high energy-efficiency reconfigurable accelerator for battery-driven mobile devices. It consists of a large processing element (PE) array without memory elements for mapping the data-flow graph of the application being executed, a small simple programmable micro-controller for data management, and a data memory. Unlike traditional coarse grained reconfigurable processors in which each PE provides registers and context memory, a CMA rduces power consumption by doing away with that for switching of hardware context and storing intermediate data in registers and their clock distribution. Although the data-flow graph mapped on the PE array is static during execution, various application programs can be implemented by making the best use of flexible data management instructions in the micro-controller. When the delay time of the PE array is shorter than the data handling time taken by the micro-controller, the supply voltage for the PE array is scaled to reduce the power consumption without degrading the performance. In contrast, when the delay time of the PE array is longer, wave pipelining is applied to enhance performance of the PE array. A prototype CMA chip (CMA-1) with 8 × 8 PE array with 24-bit data width was fabricated on the basis of 2.1 × 4.2-mm 65-nm CMOS technology, and achieves sustained performance of 2.5-GOPS/11.2-mW. This energy efficiency is comparable to that of the most-energy-efficient accelerators that have been reported.

Original languageEnglish
Title of host publication2011 International Symposium on Integrated Circuits, ISIC 2011
Pages579-584
Number of pages6
DOIs
Publication statusPublished - 2011
Event2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore
Duration: 2011 Dec 122011 Dec 14

Other

Other2011 International Symposium on Integrated Circuits, ISIC 2011
CitySingaporeSingapore
Period11/12/1211/12/14

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Combinatorial circuits
Particle accelerators
Processing
Data flow graphs
Data storage equipment
Information management
Controllers
Energy efficiency
Time delay
Electric power utilization
Data handling
Application programs
Mobile devices
Clocks
Hardware
Electric potential

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Ozaki, N., Yasuda, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., ... Kondo, M. (2011). A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS. In 2011 International Symposium on Integrated Circuits, ISIC 2011 (pp. 579-584). [6131929] https://doi.org/10.1109/ISICir.2011.6131929

A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS. / Ozaki, N.; Yasuda, Y.; Saito, Y.; Ikebuchi, D.; Kimura, M.; Amano, H.; Nakamura, H.; Usami, Kimiyoshi; Namiki, M.; Kondo, M.

2011 International Symposium on Integrated Circuits, ISIC 2011. 2011. p. 579-584 6131929.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ozaki, N, Yasuda, Y, Saito, Y, Ikebuchi, D, Kimura, M, Amano, H, Nakamura, H, Usami, K, Namiki, M & Kondo, M 2011, A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS. in 2011 International Symposium on Integrated Circuits, ISIC 2011., 6131929, pp. 579-584, 2011 International Symposium on Integrated Circuits, ISIC 2011, SingaporeSingapore, 11/12/12. https://doi.org/10.1109/ISICir.2011.6131929
Ozaki N, Yasuda Y, Saito Y, Ikebuchi D, Kimura M, Amano H et al. A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS. In 2011 International Symposium on Integrated Circuits, ISIC 2011. 2011. p. 579-584. 6131929 https://doi.org/10.1109/ISICir.2011.6131929
Ozaki, N. ; Yasuda, Y. ; Saito, Y. ; Ikebuchi, D. ; Kimura, M. ; Amano, H. ; Nakamura, H. ; Usami, Kimiyoshi ; Namiki, M. ; Kondo, M. / A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS. 2011 International Symposium on Integrated Circuits, ISIC 2011. 2011. pp. 579-584
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