A 3.5mm2, inductor-less digital-intensive radio SoC for 300-to-950MHz ISM-band applications supporting 1.0-to-240kbps multi-data-rates

Takashi Tokairin; Hiromi Saito; Haruya Ishizaki; Yoshitaka Oka; Tadashi Maeda; Seiichi Oshima; Masaaki Soda; Mitsuji Okada; Shinichi Hori; Masaki Kitsunezuka; Masayuki Mizuno

A 3.5mm², inductor-less digital-intensive radio SoC for 300-to-950MHz ISM-band applications supporting 1.0-to-240kbps multi-data-rates

Takashi Tokairin, Hiromi Saito, Haruya Ishizaki, Yoshitaka Oka, Tadashi Maeda, Seiichi Oshima, Masaaki Soda, Mitsuji Okada, Shinichi Hori, Masaki Kitsunezuka, Masayuki Mizuno

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A small-sized (less than 2mm² total analog and radio area) sub-GHz radio SoC for low power and low data-rate wireless applications is presented. The SoC has been equipped with a low-power analog-to-digital conversion scheme having a variable over-sampling ratio, multi-sampling-rate channel select filtering, and inductor-less RF front-end circuits incorporating a high output power stair-like shaping CMOS power-amplifier with a duty-imbalance-compensated level-shifter. The SoC, fabricated with 90nm CMOS, occupies only 3.5mm². It has a sensitivity of -118dBm in a 2.4kbps FSK mode for a 433MHz band, and channel selectivity for data rates ranging from 1.0 to 240kbps.

Original language	English
Title of host publication	2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
Pages	30-31
Number of pages	2
Publication status	Published - 2011 Sep 16
Externally published	Yes
Event	2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan Duration: 2011 Jun 15 → 2011 Jun 17

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2011 Symposium on VLSI Circuits, VLSIC 2011
Country/Territory	Japan
City	Kyoto
Period	11/6/15 → 11/6/17

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Tokairin, T., Saito, H., Ishizaki, H., Oka, Y., Maeda, T., Oshima, S., Soda, M., Okada, M., Hori, S., Kitsunezuka, M., & Mizuno, M. (2011). A 3.5mm², inductor-less digital-intensive radio SoC for 300-to-950MHz ISM-band applications supporting 1.0-to-240kbps multi-data-rates. In 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers (pp. 30-31). [5986409] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

A 3.5mm², inductor-less digital-intensive radio SoC for 300-to-950MHz ISM-band applications supporting 1.0-to-240kbps multi-data-rates. / Tokairin, Takashi; Saito, Hiromi; Ishizaki, Haruya et al.

2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers. 2011. p. 30-31 5986409 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tokairin, T, Saito, H, Ishizaki, H, Oka, Y, Maeda, T, Oshima, S, Soda, M, Okada, M, Hori, S, Kitsunezuka, M & Mizuno, M 2011, A 3.5mm², inductor-less digital-intensive radio SoC for 300-to-950MHz ISM-band applications supporting 1.0-to-240kbps multi-data-rates. in 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers., 5986409, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 30-31, 2011 Symposium on VLSI Circuits, VLSIC 2011, Kyoto, Japan, 11/6/15.

@inproceedings{111bee664a1e42d98ee3ba75153f149d,

title = "A 3.5mm2, inductor-less digital-intensive radio SoC for 300-to-950MHz ISM-band applications supporting 1.0-to-240kbps multi-data-rates",

abstract = "A small-sized (less than 2mm2 total analog and radio area) sub-GHz radio SoC for low power and low data-rate wireless applications is presented. The SoC has been equipped with a low-power analog-to-digital conversion scheme having a variable over-sampling ratio, multi-sampling-rate channel select filtering, and inductor-less RF front-end circuits incorporating a high output power stair-like shaping CMOS power-amplifier with a duty-imbalance-compensated level-shifter. The SoC, fabricated with 90nm CMOS, occupies only 3.5mm2. It has a sensitivity of -118dBm in a 2.4kbps FSK mode for a 433MHz band, and channel selectivity for data rates ranging from 1.0 to 240kbps.",

author = "Takashi Tokairin and Hiromi Saito and Haruya Ishizaki and Yoshitaka Oka and Tadashi Maeda and Seiichi Oshima and Masaaki Soda and Mitsuji Okada and Shinichi Hori and Masaki Kitsunezuka and Masayuki Mizuno",

year = "2011",

month = sep,

day = "16",

language = "English",

isbn = "9784863481657",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "30--31",

booktitle = "2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers",

note = "2011 Symposium on VLSI Circuits, VLSIC 2011 ; Conference date: 15-06-2011 Through 17-06-2011",

}

TY - GEN

T1 - A 3.5mm2, inductor-less digital-intensive radio SoC for 300-to-950MHz ISM-band applications supporting 1.0-to-240kbps multi-data-rates

AU - Tokairin, Takashi

AU - Saito, Hiromi

AU - Ishizaki, Haruya

AU - Oka, Yoshitaka

AU - Maeda, Tadashi

AU - Oshima, Seiichi

AU - Soda, Masaaki

AU - Okada, Mitsuji

AU - Hori, Shinichi

AU - Kitsunezuka, Masaki

AU - Mizuno, Masayuki

PY - 2011/9/16

Y1 - 2011/9/16

N2 - A small-sized (less than 2mm2 total analog and radio area) sub-GHz radio SoC for low power and low data-rate wireless applications is presented. The SoC has been equipped with a low-power analog-to-digital conversion scheme having a variable over-sampling ratio, multi-sampling-rate channel select filtering, and inductor-less RF front-end circuits incorporating a high output power stair-like shaping CMOS power-amplifier with a duty-imbalance-compensated level-shifter. The SoC, fabricated with 90nm CMOS, occupies only 3.5mm2. It has a sensitivity of -118dBm in a 2.4kbps FSK mode for a 433MHz band, and channel selectivity for data rates ranging from 1.0 to 240kbps.

AB - A small-sized (less than 2mm2 total analog and radio area) sub-GHz radio SoC for low power and low data-rate wireless applications is presented. The SoC has been equipped with a low-power analog-to-digital conversion scheme having a variable over-sampling ratio, multi-sampling-rate channel select filtering, and inductor-less RF front-end circuits incorporating a high output power stair-like shaping CMOS power-amplifier with a duty-imbalance-compensated level-shifter. The SoC, fabricated with 90nm CMOS, occupies only 3.5mm2. It has a sensitivity of -118dBm in a 2.4kbps FSK mode for a 433MHz band, and channel selectivity for data rates ranging from 1.0 to 240kbps.

UR - http://www.scopus.com/inward/record.url?scp=80052666437&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052666437&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:80052666437

SN - 9784863481657

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 30

EP - 31

BT - 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers

T2 - 2011 Symposium on VLSI Circuits, VLSIC 2011

Y2 - 15 June 2011 through 17 June 2011

ER -