A 65-nm CMOS fully integrated shock-wave antenna array with on-chip jitter and pulse-delay adjustment for millimeter-wave active imaging application

Nguyen Ngoc Mai Khanh, Masahiro Sasaki, Kunihiro Asada

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper presents a 65-nm CMOS 8-antenna array transmitter operating in 117-130-GHz range for short range and portable millimeter-wave (mm-wave) active imaging applications. Each antenna element is a new on-chip antenna located on the top metal. By using onchip transformer, pulse output of each resistor-less mm-wave pulse generators (PG) are sent to each integrated antenna. To adjust pulse delays for the purpose of pulse beam-forming, a 7-bit digitally programmable delay circuit (DPDC) is added to each of PGs. Moreover, in order to dynamically adjust pulse delays among eight SW's outputs, we implemented onchip jitter and relative skew measuring circuit with 20-bit digital output to achieve cumulative distribution (CDF) and probability density (PDF) functions from which DPDC's input codes are decided to align eight antenna's output pulses. Two measured radiation peaks after relative skew alignment are obtained at (θ, φ) angles of (-56°; 0°) and (+56°; 0°). Measurement results shows that beam-forming angles of the fully integrated antenna array can be adjusted by digital input codes and by the on-chip skew adjustment circuit for active imaging applications.

Original languageEnglish
Pages (from-to)2554-2562
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE94-A
Issue number12
DOIs
Publication statusPublished - 2011 Dec

Keywords

  • Active imaging
  • Beam-forming
  • CMOS
  • Integrated circuit
  • Jitter measurement
  • Millimeter-wave
  • On-chip antenna array
  • Wide-band

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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