A 7-Mask CMOS Process with Selective Oxide Deposition

Tadahiko Horiuchi; Tetsuya Homma; Yukinobu Murao; Koichiro Okumura

doi:10.1109/16.223705

A 7-Mask CMOS Process with Selective Oxide Deposition

Tadahiko Horiuchi, Tetsuya Homma, Yukinobu Murao, Koichiro Okumura

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

This paper describes a new 7-mask CMOS process using liquid phase oxide deposition which has selectivity against photoresist. The process modules for self-aligned well and one mask LDD formation are developed. The features of the process are 1) short TAT: 7 masks to first metallization, 2) self-aligned twin retrograde wells with 40% reduction of the p⁺-n⁺ spacing compared to conventional wells, and 3) optimal LDD design using different sidewall spacer width for n- and p-channel MOSFET’s giving a 10% larger on-current for p-channel MOSFET’s compared to a conventional process.

Original language	English
Pages (from-to)	1455-1460
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	40
Issue number	8
DOIs	https://doi.org/10.1109/16.223705
Publication status	Published - 1993 Aug
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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abstract = "This paper describes a new 7-mask CMOS process using liquid phase oxide deposition which has selectivity against photoresist. The process modules for self-aligned well and one mask LDD formation are developed. The features of the process are 1) short TAT: 7 masks to first metallization, 2) self-aligned twin retrograde wells with 40% reduction of the p+-n+ spacing compared to conventional wells, and 3) optimal LDD design using different sidewall spacer width for n- and p-channel MOSFET{\textquoteright}s giving a 10% larger on-current for p-channel MOSFET{\textquoteright}s compared to a conventional process.",

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N2 - This paper describes a new 7-mask CMOS process using liquid phase oxide deposition which has selectivity against photoresist. The process modules for self-aligned well and one mask LDD formation are developed. The features of the process are 1) short TAT: 7 masks to first metallization, 2) self-aligned twin retrograde wells with 40% reduction of the p+-n+ spacing compared to conventional wells, and 3) optimal LDD design using different sidewall spacer width for n- and p-channel MOSFET’s giving a 10% larger on-current for p-channel MOSFET’s compared to a conventional process.

AB - This paper describes a new 7-mask CMOS process using liquid phase oxide deposition which has selectivity against photoresist. The process modules for self-aligned well and one mask LDD formation are developed. The features of the process are 1) short TAT: 7 masks to first metallization, 2) self-aligned twin retrograde wells with 40% reduction of the p+-n+ spacing compared to conventional wells, and 3) optimal LDD design using different sidewall spacer width for n- and p-channel MOSFET’s giving a 10% larger on-current for p-channel MOSFET’s compared to a conventional process.

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A 7-Mask CMOS Process with Selective Oxide Deposition

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