A circuit for on-chip skew adjustment with jitter and setup time measurement

Masahiro Sasaki; Nguyen Ngoc Mai Khanh; Kunihiro Asada

doi:10.1109/ASSCC.2010.5716594

A circuit for on-chip skew adjustment with jitter and setup time measurement

Masahiro Sasaki, Nguyen Ngoc Mai Khanh, Kunihiro Asada

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

This paper reports a circuit for on-chip skew adjustment with jitter and setup time measurement. A test chip has been fabricated in a 65-nm CMOS process. It successfully measures the random jitter distribution and the relative setup time. This circuit becomes necessary in SoCs because direct measurement cannot be performed by external equipment. Setup time of a D-FF is measured by sweeping over the range of an adjustable input delay line. Its jitter is represented by a Cumulative Distribution Function which is measured by sampling the setup time repeatedly. The skew can be adjusted based on the setup time and jitter determined by our method. Furthermore, this method can be extended for almost any number of Target/Reference Programmable Delay Lines. This system enables designers to adjust skew between the distributed clock paths as well as to measure sub-picosecond level jitter and setup time of D-FFs beyond 10-GHz.

Original language	English
Title of host publication	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages	217-220
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2010.5716594
Publication status	Published - 2010 Dec 1
Externally published	Yes
Event	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China Duration: 2010 Nov 8 → 2010 Nov 10

Publication series

Name	2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Conference

Conference	2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Country	China
City	Beijing
Period	10/11/8 → 10/11/10

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ASSCC.2010.5716594

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Cite this

Sasaki, M., Khanh, N. N. M., & Asada, K. (2010). A circuit for on-chip skew adjustment with jitter and setup time measurement. In 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 (pp. 217-220). [5716594] (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010). https://doi.org/10.1109/ASSCC.2010.5716594

A circuit for on-chip skew adjustment with jitter and setup time measurement. / Sasaki, Masahiro; Khanh, Nguyen Ngoc Mai; Asada, Kunihiro.

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. p. 217-220 5716594 (2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sasaki, M, Khanh, NNM & Asada, K 2010, A circuit for on-chip skew adjustment with jitter and setup time measurement. in 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010., 5716594, 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, pp. 217-220, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, Beijing, China, 10/11/8. https://doi.org/10.1109/ASSCC.2010.5716594

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