TY - GEN
T1 - A circuit for on-chip skew adjustment with jitter and setup time measurement
AU - Sasaki, Masahiro
AU - Khanh, Nguyen Ngoc Mai
AU - Asada, Kunihiro
PY - 2010/12/1
Y1 - 2010/12/1
N2 - This paper reports a circuit for on-chip skew adjustment with jitter and setup time measurement. A test chip has been fabricated in a 65-nm CMOS process. It successfully measures the random jitter distribution and the relative setup time. This circuit becomes necessary in SoCs because direct measurement cannot be performed by external equipment. Setup time of a D-FF is measured by sweeping over the range of an adjustable input delay line. Its jitter is represented by a Cumulative Distribution Function which is measured by sampling the setup time repeatedly. The skew can be adjusted based on the setup time and jitter determined by our method. Furthermore, this method can be extended for almost any number of Target/Reference Programmable Delay Lines. This system enables designers to adjust skew between the distributed clock paths as well as to measure sub-picosecond level jitter and setup time of D-FFs beyond 10-GHz.
AB - This paper reports a circuit for on-chip skew adjustment with jitter and setup time measurement. A test chip has been fabricated in a 65-nm CMOS process. It successfully measures the random jitter distribution and the relative setup time. This circuit becomes necessary in SoCs because direct measurement cannot be performed by external equipment. Setup time of a D-FF is measured by sweeping over the range of an adjustable input delay line. Its jitter is represented by a Cumulative Distribution Function which is measured by sampling the setup time repeatedly. The skew can be adjusted based on the setup time and jitter determined by our method. Furthermore, this method can be extended for almost any number of Target/Reference Programmable Delay Lines. This system enables designers to adjust skew between the distributed clock paths as well as to measure sub-picosecond level jitter and setup time of D-FFs beyond 10-GHz.
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U2 - 10.1109/ASSCC.2010.5716594
DO - 10.1109/ASSCC.2010.5716594
M3 - Conference contribution
AN - SCOPUS:79952853236
SN - 9781424482979
T3 - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
SP - 217
EP - 220
BT - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
T2 - 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Y2 - 8 November 2010 through 10 November 2010
ER -