A circuit for on-chip skew adjustment with jitter and setup time measurement

Masahiro Sasaki, Nguyen Ngoc Mai Khanh, Kunihiro Asada

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

This paper reports a circuit for on-chip skew adjustment with jitter and setup time measurement. A test chip has been fabricated in a 65-nm CMOS process. It successfully measures the random jitter distribution and the relative setup time. This circuit becomes necessary in SoCs because direct measurement cannot be performed by external equipment. Setup time of a D-FF is measured by sweeping over the range of an adjustable input delay line. Its jitter is represented by a Cumulative Distribution Function which is measured by sampling the setup time repeatedly. The skew can be adjusted based on the setup time and jitter determined by our method. Furthermore, this method can be extended for almost any number of Target/Reference Programmable Delay Lines. This system enables designers to adjust skew between the distributed clock paths as well as to measure sub-picosecond level jitter and setup time of D-FFs beyond 10-GHz.

Original languageEnglish
Title of host publication2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages217-220
Number of pages4
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing
Duration: 2010 Nov 82010 Nov 10

Other

Other2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
CityBeijing
Period10/11/810/11/10

Fingerprint

Time measurement
Jitter
Networks (circuits)
Electric delay lines
Distribution functions
Clocks
Sampling

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Sasaki, M., Khanh, N. N. M., & Asada, K. (2010). A circuit for on-chip skew adjustment with jitter and setup time measurement. In 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 (pp. 217-220). [5716594] https://doi.org/10.1109/ASSCC.2010.5716594

A circuit for on-chip skew adjustment with jitter and setup time measurement. / Sasaki, Masahiro; Khanh, Nguyen Ngoc Mai; Asada, Kunihiro.

2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. p. 217-220 5716594.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sasaki, M, Khanh, NNM & Asada, K 2010, A circuit for on-chip skew adjustment with jitter and setup time measurement. in 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010., 5716594, pp. 217-220, 2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010, Beijing, 10/11/8. https://doi.org/10.1109/ASSCC.2010.5716594
Sasaki M, Khanh NNM, Asada K. A circuit for on-chip skew adjustment with jitter and setup time measurement. In 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. p. 217-220. 5716594 https://doi.org/10.1109/ASSCC.2010.5716594
Sasaki, Masahiro ; Khanh, Nguyen Ngoc Mai ; Asada, Kunihiro. / A circuit for on-chip skew adjustment with jitter and setup time measurement. 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010. 2010. pp. 217-220
@inproceedings{46ca3dff479a4730a74f1c9b4c3b6656,
title = "A circuit for on-chip skew adjustment with jitter and setup time measurement",
abstract = "This paper reports a circuit for on-chip skew adjustment with jitter and setup time measurement. A test chip has been fabricated in a 65-nm CMOS process. It successfully measures the random jitter distribution and the relative setup time. This circuit becomes necessary in SoCs because direct measurement cannot be performed by external equipment. Setup time of a D-FF is measured by sweeping over the range of an adjustable input delay line. Its jitter is represented by a Cumulative Distribution Function which is measured by sampling the setup time repeatedly. The skew can be adjusted based on the setup time and jitter determined by our method. Furthermore, this method can be extended for almost any number of Target/Reference Programmable Delay Lines. This system enables designers to adjust skew between the distributed clock paths as well as to measure sub-picosecond level jitter and setup time of D-FFs beyond 10-GHz.",
author = "Masahiro Sasaki and Khanh, {Nguyen Ngoc Mai} and Kunihiro Asada",
year = "2010",
doi = "10.1109/ASSCC.2010.5716594",
language = "English",
isbn = "9781424482979",
pages = "217--220",
booktitle = "2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010",

}

TY - GEN

T1 - A circuit for on-chip skew adjustment with jitter and setup time measurement

AU - Sasaki, Masahiro

AU - Khanh, Nguyen Ngoc Mai

AU - Asada, Kunihiro

PY - 2010

Y1 - 2010

N2 - This paper reports a circuit for on-chip skew adjustment with jitter and setup time measurement. A test chip has been fabricated in a 65-nm CMOS process. It successfully measures the random jitter distribution and the relative setup time. This circuit becomes necessary in SoCs because direct measurement cannot be performed by external equipment. Setup time of a D-FF is measured by sweeping over the range of an adjustable input delay line. Its jitter is represented by a Cumulative Distribution Function which is measured by sampling the setup time repeatedly. The skew can be adjusted based on the setup time and jitter determined by our method. Furthermore, this method can be extended for almost any number of Target/Reference Programmable Delay Lines. This system enables designers to adjust skew between the distributed clock paths as well as to measure sub-picosecond level jitter and setup time of D-FFs beyond 10-GHz.

AB - This paper reports a circuit for on-chip skew adjustment with jitter and setup time measurement. A test chip has been fabricated in a 65-nm CMOS process. It successfully measures the random jitter distribution and the relative setup time. This circuit becomes necessary in SoCs because direct measurement cannot be performed by external equipment. Setup time of a D-FF is measured by sweeping over the range of an adjustable input delay line. Its jitter is represented by a Cumulative Distribution Function which is measured by sampling the setup time repeatedly. The skew can be adjusted based on the setup time and jitter determined by our method. Furthermore, this method can be extended for almost any number of Target/Reference Programmable Delay Lines. This system enables designers to adjust skew between the distributed clock paths as well as to measure sub-picosecond level jitter and setup time of D-FFs beyond 10-GHz.

UR - http://www.scopus.com/inward/record.url?scp=79952853236&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79952853236&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2010.5716594

DO - 10.1109/ASSCC.2010.5716594

M3 - Conference contribution

SN - 9781424482979

SP - 217

EP - 220

BT - 2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

ER -