A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's

Tadashi Maeda; Keiichi Numata; Masatoshi Tokushima; Masaoki Ishikawa; Muneo Fukaishi; Hikaru Hida; Yasuo Ohno

doi:10.1109/4.488001

A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's

Tadashi Maeda, Keiichi Numata, Masatoshi Tokushima, Masaoki Ishikawa, Muneo Fukaishi, Hikaru Hida, Yasuo Ohno

Department of Electronic Engineering

Research output: Contribution to journal › Article

4 Citations (Scopus)

Abstract

This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSI's. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value reported for D-FF's so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.

Original language	English
Pages (from-to)	240-246
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	31
Issue number	2
DOIs	https://doi.org/10.1109/4.488001
Publication status	Published - 1996 Feb 1

ASJC Scopus subject areas

Electrical and Electronic Engineering

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Maeda, T., Numata, K., Tokushima, M., Ishikawa, M., Fukaishi, M., Hida, H., & Ohno, Y. (1996). A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's. IEEE Journal of Solid-State Circuits, 31(2), 240-246. https://doi.org/10.1109/4.488001

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abstract = "This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSI's. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value reported for D-FF's so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.",

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AU - Ishikawa, Masaoki

AU - Fukaishi, Muneo

AU - Hida, Hikaru

AU - Ohno, Yasuo

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AB - This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSI's. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value reported for D-FF's so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.

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