Abstract
This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSI's. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value reported for D-FF's so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.
| Original language | English |
|---|---|
| Pages (from-to) | 240-246 |
| Number of pages | 7 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 31 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 1996 Feb |
| Externally published | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's. / Maeda, Tadashi; Numata, Keiichi; Tokushima, Masatoshi; Ishikawa, Masaoki; Fukaishi, Muneo; Hida, Hikaru; Ohno, Yasuo.
In: IEEE Journal of Solid-State Circuits, Vol. 31, No. 2, 02.1996, p. 240-246.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's
AU - Maeda, Tadashi
AU - Numata, Keiichi
AU - Tokushima, Masatoshi
AU - Ishikawa, Masaoki
AU - Fukaishi, Muneo
AU - Hida, Hikaru
AU - Ohno, Yasuo
PY - 1996/2
Y1 - 1996/2
N2 - This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSI's. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value reported for D-FF's so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.
AB - This paper describes a low-supply-voltage flip flop circuit design. The advantages of low supply voltage are discussed. Based on an analytical circuit delay model, conventional flip flop operating speed degradation below 1 V supply voltage is analyzed. We then propose a new GaAs static flip flop, called TD-FF (tri-state driver flip-flop), for ultra-low supply voltage GaAs heterojunction FET LSI's. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value reported for D-FF's so far. We also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.
UR - http://www.scopus.com/inward/record.url?scp=0030082587&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0030082587&partnerID=8YFLogxK
U2 - 10.1109/4.488001
DO - 10.1109/4.488001
M3 - Article
AN - SCOPUS:0030082587
VL - 31
SP - 240
EP - 246
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 2
ER -