A highly linear open-loop full CMOS high-speed sample-and-hold stage

Khayrollah Hadidi, Masahiro Sasaki, Tadatoshi Watanabe, Daigo Muramatsu, Takashi Matsumoto

Research output: Contribution to journalArticlepeer-review


Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 μm digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.

Original languageEnglish
Pages (from-to)261-266
Number of pages6
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number2
Publication statusPublished - 2000 Jan 1
Externally publishedYes


  • CMOS buffers
  • Full CMOS S/H
  • Open-loop S/H
  • S/H
  • Sample-and-hold

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


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