Abstract
Based on a cascode-driver source-follower buffer, and a passive sampling architecture, we have implemented a differential sample-and-hold circuit in a 0.8 μm digital CMOS process. The buffer which eliminates channel length modulation of the driver device behaves very linearly, in low frequencies or sampled-data applications. This is the main reason that this first open-loop CMOS sample-and-hold can achieves very high linearity while functions at very high sampling rate. The circuit achieved -61 dB THD for a 1.42 Vp-p 10 MHz input signal at a 103 MHz sampling rate and -55.9 dB THD for a 1.22 Vp-p 20 MHz at a 101 MHz sampling rate.
| Original language | English |
|---|---|
| Pages (from-to) | 261-266 |
| Number of pages | 6 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E82-A |
| Issue number | 2 |
| Publication status | Published - 2000 Jan 1 |
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Keywords
- CMOS buffers
- Full CMOS S/H
- Open-loop S/H
- S/H
- Sample-and-hold
ASJC Scopus subject areas
- Signal Processing
- Computer Graphics and Computer-Aided Design
- Electrical and Electronic Engineering
- Applied Mathematics
Cite this
Hadidi, K., Sasaki, M., Watanabe, T., Muramatsu, D., & Matsumoto, T. (2000). A highly linear open-loop full CMOS high-speed sample-and-hold stage. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E82-A(2), 261-266.