A logarithmic compression ADC using transient response of a comparator

Yuji Inagaki, Yusaku Sugimori, Eri Ioka, Yasuyuki Matsuya

Research output: Contribution to journalArticle

Abstract

This paper describes a logarithmic compression ADC using a subranging TDC and the transient response of a comparator. We utilized the settling time of the comparator for a logarithmic compression instead of a logarithmic amplifier. The settling time of the comparator is inversely proportional to the logarithm of an input voltage. In the proposed ADC, an input voltage is converted into a pulse whose width represents the settling time of the comparator. Subsequently, the TDC converts the pulse width into a binary code. The supply voltage of the proposed ADC can be reduced more than a conventional logarithmic ADC because an analog to digital conversion takes place in the time domain. We confirmed through a 0.18-μm CMOS circuit simulation that the proposed ADC achieves a resolution of 11 bits, a sampling rate of 20 MS/s, a dynamic range of 59 dB and a power consumption of 9.8 mW at 1.5 V operation.

Original languageEnglish
Pages (from-to)359-362
Number of pages4
JournalIEICE Transactions on Electronics
VolumeE100C
Issue number4
DOIs
Publication statusPublished - 2017 Apr
Externally publishedYes

Keywords

  • ADC
  • Latched comparator
  • Logarithmic compression
  • Settling time
  • Subranging
  • TDC

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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