A low-power dual-band triple-mode WLAN CMOS Transceiver

Tadashi Maeda, Noriaki Matsuno, Shinichi Hori, Tomoyuki Yamase, Takashi Tokairin, Kiyoshi Yanagisawa, Hitoshi Yano, Robert Walkington, Keiichi Numata, Nobuhide Yoshida, Yuji Takahashi, Hikaru Hida

Research output: Contribution to journalArticlepeer-review

33 Citations (Scopus)


This paper describes a 0.18-μm CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a ∑Δ-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode - both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 dB, a sensitivity of -931-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively.

Original languageEnglish
Article number1717671
Pages (from-to)2481-2489
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number11
Publication statusPublished - 2006 Nov
Externally publishedYes


  • Complementary metal-oxide semiconductor (CMOS) transceiver
  • Dual-band
  • Frequency synthesizer
  • IEEE802.11a/b/g
  • Low-noise amplifier (LNA)
  • Low-pass filter (LPF)
  • Orthogonal frequency division multiplexing (OFDM)
  • Triple-mode

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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