A low power matched filter for DS-CDMA based on analog signal processing

Masahiro Sasaki; Takeyasu Sakai; Takashi Matsumoto

A low power matched filter for DS-CDMA based on analog signal processing

Masahiro Sasaki, Takeyasu Sakai, Takashi Matsumoto

Research output: Contribution to journal › Article › peer-review

Abstract

This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm². The proposed circuit will thus be a useful LSI for mobile terminals.

Original language	English
Pages (from-to)	752-757
Number of pages	6
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E86-A
Issue number	4
Publication status	Published - 2003 Apr
Externally published	Yes

Keywords

Analog circuit
DS-CDMA
Matched filter
Multiply-and-accumulate operation
Spread spectrum
Weighted-sum operation

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

Fingerprint Dive into the research topics of 'A low power matched filter for DS-CDMA based on analog signal processing'. Together they form a unique fingerprint.

Cite this

@article{3a8428dd76bd48faaf7970c06b61689a,

title = "A low power matched filter for DS-CDMA based on analog signal processing",

abstract = "This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.",

keywords = "Analog circuit, DS-CDMA, Matched filter, Multiply-and-accumulate operation, Spread spectrum, Weighted-sum operation",

author = "Masahiro Sasaki and Takeyasu Sakai and Takashi Matsumoto",

year = "2003",

month = apr,

language = "English",

volume = "E86-A",

pages = "752--757",

journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",

issn = "0916-8508",

publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",

number = "4",

}

TY - JOUR

T1 - A low power matched filter for DS-CDMA based on analog signal processing

AU - Sasaki, Masahiro

AU - Sakai, Takeyasu

AU - Matsumoto, Takashi

PY - 2003/4

Y1 - 2003/4

N2 - This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.

AB - This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.

KW - Analog circuit

KW - DS-CDMA

KW - Matched filter

KW - Multiply-and-accumulate operation

KW - Spread spectrum

KW - Weighted-sum operation

UR - http://www.scopus.com/inward/record.url?scp=0142227879&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0142227879&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0142227879

VL - E86-A

SP - 752

EP - 757

JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

SN - 0916-8508

IS - 4

ER -