A low power matched filter for DS-CDMA based on analog signal processing

Masahiro Sasaki; Takeyasu Sakai; Takashi Matsumoto

A low power matched filter for DS-CDMA based on analog signal processing

Masahiro Sasaki, Takeyasu Sakai, Takashi Matsumoto

Research output: Contribution to journal › Article › peer-review

Abstract

This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm². The proposed circuit will thus be a useful LSI for mobile terminals.

Original language	English
Pages (from-to)	752-757
Number of pages	6
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E86-A
Issue number	4
Publication status	Published - 2003 Apr
Externally published	Yes

Keywords

Analog circuit
DS-CDMA
Matched filter
Multiply-and-accumulate operation
Spread spectrum
Weighted-sum operation

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

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abstract = "This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.",

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AU - Sakai, Takeyasu

AU - Matsumoto, Takashi

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N2 - This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.

AB - This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.

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KW - Multiply-and-accumulate operation

KW - Spread spectrum

KW - Weighted-sum operation

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A low power matched filter for DS-CDMA based on analog signal processing

Abstract

Keywords

ASJC Scopus subject areas

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