Abstract
This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.
| Original language | English |
|---|---|
| Pages (from-to) | 752-757 |
| Number of pages | 6 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E86-A |
| Issue number | 4 |
| Publication status | Published - 2003 Apr |
| Externally published | Yes |
Fingerprint
Keywords
- Analog circuit
- DS-CDMA
- Matched filter
- Multiply-and-accumulate operation
- Spread spectrum
- Weighted-sum operation
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
- Information Systems
Cite this
A low power matched filter for DS-CDMA based on analog signal processing. / Sasaki, Masahiro; Sakai, Takeyasu; Matsumoto, Takashi.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E86-A, No. 4, 04.2003, p. 752-757.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A low power matched filter for DS-CDMA based on analog signal processing
AU - Sasaki, Masahiro
AU - Sakai, Takeyasu
AU - Matsumoto, Takashi
PY - 2003/4
Y1 - 2003/4
N2 - This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.
AB - This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.
KW - Analog circuit
KW - DS-CDMA
KW - Matched filter
KW - Multiply-and-accumulate operation
KW - Spread spectrum
KW - Weighted-sum operation
UR - http://www.scopus.com/inward/record.url?scp=0142227879&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0142227879&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0142227879
VL - E86-A
SP - 752
EP - 757
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 4
ER -