A low power matched filter for DS-CDMA based on analog signal processing

Masahiro Sasaki, Takeyasu Sakai, Takashi Matsumoto

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

This paper proposes a low power consumption Analog Matched Filter (AMF) that utilizes capacitor multiply-and-accumulate operations. A high-speed, high-precision Analog-to-Digital (A/D) converter is unnecessary because the proposed circuit directly samples received analog signals. A code-shifting MF structure is used to prevent errors from accumulating. A 15-tap AMF circuit was fabricated using 0.35 μm CMOS technology. Power consumption for the 128-tap circuit is estimated to be 22.3 mW at 25 MHz and 3.3 V, and the area is estimated to be 0.33 mm2. The proposed circuit will thus be a useful LSI for mobile terminals.

Original languageEnglish
Pages (from-to)752-757
Number of pages6
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE86-A
Issue number4
Publication statusPublished - 2003 Apr
Externally publishedYes

Fingerprint

Matched filters
Code division multiple access
Signal processing
Networks (circuits)
Electric power utilization
Digital to analog conversion
Capacitors

Keywords

  • Analog circuit
  • DS-CDMA
  • Matched filter
  • Multiply-and-accumulate operation
  • Spread spectrum
  • Weighted-sum operation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Information Systems

Cite this

A low power matched filter for DS-CDMA based on analog signal processing. / Sasaki, Masahiro; Sakai, Takeyasu; Matsumoto, Takashi.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E86-A, No. 4, 04.2003, p. 752-757.

Research output: Contribution to journalArticle

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