A new DC-offset and I/Q-mismatch compensation technique for a CMOS direct-conversion WLAN transmitter

Kiyoshi Yanagisawa, Noriaki Matsuno, Tadashi Maeda, Shinichi Tanaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This paper presents a novel DC-offset and I/Q-mismatch compensation technique with short convergence time, high accuracy, and low-circuit-complexity In this technique, all kinds of transmitter nonidealities, i.e. an offset and a mismatch, can be detected using adequate pair of DC test signals. The test signals are designed so that the envelope of the modulator RF outputs for each test signal fluctuates when the offset or mismatch exists. The fluctuations are converted to a baseband signal using an envelope detector which is designed as a signal dynamic range compressor to avoid saturation in following stages. The polarity of this fluctuation is detected by a comparator instead of a multi-bit analog to digital converter, and a binary-search-type algorithm optimizes parameters for the offset and mismatch compensation using the 1-bit comparator output. This technique was demonstrated in a 0.18-μm CMOS 5-GHz-band WLAN transmitter. The DC offset was suppressed to -43 dBc and the image tone was suppressed to -49 dBc.

Original languageEnglish
Title of host publicationIEEE MTT-S International Microwave Symposium Digest
Pages85-88
Number of pages4
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event2007 IEEE MTT-S International Microwave Symposium, IMS 2007 - Honolulu, HI
Duration: 2007 Jun 32007 Jun 8

Other

Other2007 IEEE MTT-S International Microwave Symposium, IMS 2007
CityHonolulu, HI
Period07/6/307/6/8

Fingerprint

Wireless local area networks (WLAN)
transmitters
Transmitters
CMOS
direct current
Digital to analog conversion
Modulators
Compressors
Detectors
envelopes
Networks (circuits)
output
analog to digital converters
compressors
dynamic range
modulators
polarity
Compensation and Redress
saturation
detectors

Keywords

  • DC offset
  • Direct conversion
  • I/Q mismatch
  • Transmitters

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Yanagisawa, K., Matsuno, N., Maeda, T., & Tanaka, S. (2007). A new DC-offset and I/Q-mismatch compensation technique for a CMOS direct-conversion WLAN transmitter. In IEEE MTT-S International Microwave Symposium Digest (pp. 85-88). [4263747] https://doi.org/10.1109/MWSYM.2007.380260

A new DC-offset and I/Q-mismatch compensation technique for a CMOS direct-conversion WLAN transmitter. / Yanagisawa, Kiyoshi; Matsuno, Noriaki; Maeda, Tadashi; Tanaka, Shinichi.

IEEE MTT-S International Microwave Symposium Digest. 2007. p. 85-88 4263747.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yanagisawa, K, Matsuno, N, Maeda, T & Tanaka, S 2007, A new DC-offset and I/Q-mismatch compensation technique for a CMOS direct-conversion WLAN transmitter. in IEEE MTT-S International Microwave Symposium Digest., 4263747, pp. 85-88, 2007 IEEE MTT-S International Microwave Symposium, IMS 2007, Honolulu, HI, 07/6/3. https://doi.org/10.1109/MWSYM.2007.380260
Yanagisawa, Kiyoshi ; Matsuno, Noriaki ; Maeda, Tadashi ; Tanaka, Shinichi. / A new DC-offset and I/Q-mismatch compensation technique for a CMOS direct-conversion WLAN transmitter. IEEE MTT-S International Microwave Symposium Digest. 2007. pp. 85-88
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