A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Shiro Kamohara, Nobuyuki Sugii, Koichiro Ishibashi, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong Kha Pham

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Presents a conference poster that addresses a perpetuum mobile 32bit central processing unit that resides on 65nm CMOS technology using reverse-body-bias via assisted sleep mode.

Original languageEnglish
Title of host publication2014 IEEE Hot Chips 26 Symposium, HCS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467388832
DOIs
Publication statusPublished - 2016 May 25
Event26th IEEE Hot Chips Symposium, HCS 2014 - Cupertino, United States
Duration: 2014 Aug 10 → 2014 Aug 12

Other

Other26th IEEE Hot Chips Symposium, HCS 2014
CountryUnited States
CityCupertino
Period14/8/10 → 14/8/12

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

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    Kamohara, S., Sugii, N., Ishibashi, K., Usami, K., Amano, H., Kobayashi, K., & Pham, C. K. (2016). A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode. In 2014 IEEE Hot Chips 26 Symposium, HCS 2014 [7478838] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HOTCHIPS.2014.7478838