Abstract
A robust embedded ladder-oxide {k = 2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 μm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 μm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO 2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.
| Original language | English |
|---|---|
| Pages (from-to) | 954-961 |
| Number of pages | 8 |
| Journal | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
| Volume | 46 |
| Issue number | 3 A |
| DOIs | |
| Publication status | Published - 2007 Mar 8 |
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Keywords
- 0.13μm node
- CMOS
- Complementary metal oxide semiconductor
- Copper plug
- Cu interconnect
- Ladder-oxide
- Low-k
- Single damascene
ASJC Scopus subject areas
- Physics and Astronomy (miscellaneous)
Cite this
A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm complementary metal oxide semiconductor generation. / Oda, Noriaki; Ito, Shinya; Takewaki, Toshiyuki; Shiba, Kazutoshi; Kunishima, Hiroyuki; Hironaga, Nobuo; Honma, Ichiro; Nanba, Hiroaki; Yokogawa, Shinji; Kameyama, Akiko; Goto, Takayuki; Usami, Tatsuya; Ohto, Koichi; Kubo, Akira; Suzuki, Mieko; Yamamoto, Yoshiaki; Watanabe, Susumu; Yamada, Kenta; Ikeda, Masahiro; Ueno, Kazuyoshi; Horiuchi, Tadahiko.
In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 46, No. 3 A, 08.03.2007, p. 954-961.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm complementary metal oxide semiconductor generation
AU - Oda, Noriaki
AU - Ito, Shinya
AU - Takewaki, Toshiyuki
AU - Shiba, Kazutoshi
AU - Kunishima, Hiroyuki
AU - Hironaga, Nobuo
AU - Honma, Ichiro
AU - Nanba, Hiroaki
AU - Yokogawa, Shinji
AU - Kameyama, Akiko
AU - Goto, Takayuki
AU - Usami, Tatsuya
AU - Ohto, Koichi
AU - Kubo, Akira
AU - Suzuki, Mieko
AU - Yamamoto, Yoshiaki
AU - Watanabe, Susumu
AU - Yamada, Kenta
AU - Ikeda, Masahiro
AU - Ueno, Kazuyoshi
AU - Horiuchi, Tadahiko
PY - 2007/3/8
Y1 - 2007/3/8
N2 - A robust embedded ladder-oxide {k = 2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 μm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 μm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO 2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.
AB - A robust embedded ladder-oxide {k = 2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 μm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 μm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO 2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.
KW - 0.13μm node
KW - CMOS
KW - Complementary metal oxide semiconductor
KW - Copper plug
KW - Cu interconnect
KW - Ladder-oxide
KW - Low-k
KW - Single damascene
UR - http://www.scopus.com/inward/record.url?scp=34547885443&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34547885443&partnerID=8YFLogxK
U2 - 10.1143/JJAP.46.954
DO - 10.1143/JJAP.46.954
M3 - Article
AN - SCOPUS:34547885443
VL - 46
SP - 954
EP - 961
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
SN - 0021-4922
IS - 3 A
ER -