Abstract
A robust embedded ladder-oxide {k = 2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 μm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 μm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO 2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.
Original language | English |
---|---|
Pages (from-to) | 954-961 |
Number of pages | 8 |
Journal | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
Volume | 46 |
Issue number | 3 A |
DOIs | |
Publication status | Published - 2007 Mar 8 |
Keywords
- 0.13μm node
- CMOS
- Complementary metal oxide semiconductor
- Copper plug
- Cu interconnect
- Ladder-oxide
- Low-k
- Single damascene
ASJC Scopus subject areas
- Engineering(all)
- Physics and Astronomy(all)