Abstract
According to the growth of Internet, an IP(Internet Protocol) router with capacity of terabit/sec is required in the near future. To achieve high capacity, switch fabric should handle many pairs of input ports and output ports. For this purpose, switch of multistage network is required. This paper presents a new scalable multistage packet switch using deflection routing and shortest path routing multistage network. Deflection routing multistage network have advantage of hardware simplicity since switch element has no buffer memory, and variable length packet switching can be easily handled. Furthermore, in the proposed new interconnection method between switch elements, required amount of hardware is reduced compared with conventional switch based on the deflection routing principle. A circuit of 8 × 8 variable length packet switch element is designed on FPGA, and required amount of hardware to realize a 64 × 64 multistage network is calculated. It is shown that 64 × 64 switch will be implemented within one LSI chip, and that 10 Tbps is switch is realized by two-stage interconnection of the LSI chips.
| Original language | English |
|---|---|
| Title of host publication | IEEE International Conference on Communications |
| Pages | 2179-2185 |
| Number of pages | 7 |
| Volume | 4 |
| Publication status | Published - 2002 |
| Externally published | Yes |
| Event | 2002 International Conference on Communications (ICC 2002) - New York, NY, United States Duration: 2002 Apr 28 → 2002 May 2 |
Other
| Other | 2002 International Conference on Communications (ICC 2002) |
|---|---|
| Country | United States |
| City | New York, NY |
| Period | 02/4/28 → 02/5/2 |
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ASJC Scopus subject areas
- Media Technology
Cite this
A scalable multistage packet switch for terabit IP router based on deflection routing and shortest path routing. / Morino, Hiroaki; Thach Bao, Thai; Hoaison, Nguyen; Aida, Hitoshi; Saito, Tadao.
IEEE International Conference on Communications. Vol. 4 2002. p. 2179-2185.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A scalable multistage packet switch for terabit IP router based on deflection routing and shortest path routing
AU - Morino, Hiroaki
AU - Thach Bao, Thai
AU - Hoaison, Nguyen
AU - Aida, Hitoshi
AU - Saito, Tadao
PY - 2002
Y1 - 2002
N2 - According to the growth of Internet, an IP(Internet Protocol) router with capacity of terabit/sec is required in the near future. To achieve high capacity, switch fabric should handle many pairs of input ports and output ports. For this purpose, switch of multistage network is required. This paper presents a new scalable multistage packet switch using deflection routing and shortest path routing multistage network. Deflection routing multistage network have advantage of hardware simplicity since switch element has no buffer memory, and variable length packet switching can be easily handled. Furthermore, in the proposed new interconnection method between switch elements, required amount of hardware is reduced compared with conventional switch based on the deflection routing principle. A circuit of 8 × 8 variable length packet switch element is designed on FPGA, and required amount of hardware to realize a 64 × 64 multistage network is calculated. It is shown that 64 × 64 switch will be implemented within one LSI chip, and that 10 Tbps is switch is realized by two-stage interconnection of the LSI chips.
AB - According to the growth of Internet, an IP(Internet Protocol) router with capacity of terabit/sec is required in the near future. To achieve high capacity, switch fabric should handle many pairs of input ports and output ports. For this purpose, switch of multistage network is required. This paper presents a new scalable multistage packet switch using deflection routing and shortest path routing multistage network. Deflection routing multistage network have advantage of hardware simplicity since switch element has no buffer memory, and variable length packet switching can be easily handled. Furthermore, in the proposed new interconnection method between switch elements, required amount of hardware is reduced compared with conventional switch based on the deflection routing principle. A circuit of 8 × 8 variable length packet switch element is designed on FPGA, and required amount of hardware to realize a 64 × 64 multistage network is calculated. It is shown that 64 × 64 switch will be implemented within one LSI chip, and that 10 Tbps is switch is realized by two-stage interconnection of the LSI chips.
UR - http://www.scopus.com/inward/record.url?scp=0036283236&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0036283236&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0036283236
VL - 4
SP - 2179
EP - 2185
BT - IEEE International Conference on Communications
ER -