A scalable multistage packet switch for terabit IP router based on deflection routing and shortest path routing

Hiroaki Morino, Thai Thach Bao, Nguyen Hoaison, Hitoshi Aida, Tadao Saito

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

According to the growth of Internet, an IP(Internet Protocol) router with capacity of terabit/sec is required in the near future. To achieve high capacity, switch fabric should handle many pairs of input ports and output ports. For this purpose, switch of multistage network is required. This paper presents a new scalable multistage packet switch using deflection routing and shortest path routing multistage network. Deflection routing multistage network have advantage of hardware simplicity since switch element has no buffer memory, and variable length packet switching can be easily handled. Furthermore, in the proposed new interconnection method between switch elements, required amount of hardware is reduced compared with conventional switch based on the deflection routing principle. A circuit of 8 × 8 variable length packet switch element is designed on FPGA, and required amount of hardware to realize a 64 × 64 multistage network is calculated. It is shown that 64 × 64 switch will be implemented within one LSI chip, and that 10 Tbps is switch is realized by two-stage interconnection of the LSI chips.

Original languageEnglish
Title of host publicationIEEE International Conference on Communications
Pages2179-2185
Number of pages7
Volume4
Publication statusPublished - 2002
Externally publishedYes
Event2002 International Conference on Communications (ICC 2002) - New York, NY, United States
Duration: 2002 Apr 282002 May 2

Other

Other2002 International Conference on Communications (ICC 2002)
CountryUnited States
CityNew York, NY
Period02/4/2802/5/2

Fingerprint

Internet protocols
Routers
Switches
Network routing
Hardware
Packet switching
Computer hardware
Field programmable gate arrays (FPGA)
Internet
Data storage equipment
Networks (circuits)

ASJC Scopus subject areas

  • Media Technology

Cite this

Morino, H., Thach Bao, T., Hoaison, N., Aida, H., & Saito, T. (2002). A scalable multistage packet switch for terabit IP router based on deflection routing and shortest path routing. In IEEE International Conference on Communications (Vol. 4, pp. 2179-2185)

A scalable multistage packet switch for terabit IP router based on deflection routing and shortest path routing. / Morino, Hiroaki; Thach Bao, Thai; Hoaison, Nguyen; Aida, Hitoshi; Saito, Tadao.

IEEE International Conference on Communications. Vol. 4 2002. p. 2179-2185.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Morino, H, Thach Bao, T, Hoaison, N, Aida, H & Saito, T 2002, A scalable multistage packet switch for terabit IP router based on deflection routing and shortest path routing. in IEEE International Conference on Communications. vol. 4, pp. 2179-2185, 2002 International Conference on Communications (ICC 2002), New York, NY, United States, 02/4/28.
Morino H, Thach Bao T, Hoaison N, Aida H, Saito T. A scalable multistage packet switch for terabit IP router based on deflection routing and shortest path routing. In IEEE International Conference on Communications. Vol. 4. 2002. p. 2179-2185
Morino, Hiroaki ; Thach Bao, Thai ; Hoaison, Nguyen ; Aida, Hitoshi ; Saito, Tadao. / A scalable multistage packet switch for terabit IP router based on deflection routing and shortest path routing. IEEE International Conference on Communications. Vol. 4 2002. pp. 2179-2185
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