TY - JOUR
T1 - A scalable multistage packet switch for terabit IP router based on deflection routing and shortest path routing
AU - Morino, Hiroaki
AU - Thach Bao, Thai
AU - Hoaison, Nguyen
AU - Aida, Hitoshi
AU - Saito, Tadao
PY - 2002/1/1
Y1 - 2002/1/1
N2 - According to the growth of Internet, an IP(Internet Protocol) router with capacity of terabit/sec is required in the near future. To achieve high capacity, switch fabric should handle many pairs of input ports and output ports. For this purpose, switch of multistage network is required. This paper presents a new scalable multistage packet switch using deflection routing and shortest path routing multistage network. Deflection routing multistage network have advantage of hardware simplicity since switch element has no buffer memory, and variable length packet switching can be easily handled. Furthermore, in the proposed new interconnection method between switch elements, required amount of hardware is reduced compared with conventional switch based on the deflection routing principle. A circuit of 8 × 8 variable length packet switch element is designed on FPGA, and required amount of hardware to realize a 64 × 64 multistage network is calculated. It is shown that 64 × 64 switch will be implemented within one LSI chip, and that 10 Tbps is switch is realized by two-stage interconnection of the LSI chips.
AB - According to the growth of Internet, an IP(Internet Protocol) router with capacity of terabit/sec is required in the near future. To achieve high capacity, switch fabric should handle many pairs of input ports and output ports. For this purpose, switch of multistage network is required. This paper presents a new scalable multistage packet switch using deflection routing and shortest path routing multistage network. Deflection routing multistage network have advantage of hardware simplicity since switch element has no buffer memory, and variable length packet switching can be easily handled. Furthermore, in the proposed new interconnection method between switch elements, required amount of hardware is reduced compared with conventional switch based on the deflection routing principle. A circuit of 8 × 8 variable length packet switch element is designed on FPGA, and required amount of hardware to realize a 64 × 64 multistage network is calculated. It is shown that 64 × 64 switch will be implemented within one LSI chip, and that 10 Tbps is switch is realized by two-stage interconnection of the LSI chips.
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U2 - 10.1109/ICC.2002.997233
DO - 10.1109/ICC.2002.997233
M3 - Article
AN - SCOPUS:0036283236
VL - 4
SP - 2179
EP - 2185
JO - Conference Record - International Conference on Communications
JF - Conference Record - International Conference on Communications
SN - 0536-1486
ER -