A scalable multistage packet switch for terabit IP router based on deflection routing and shortest path routing

Hiroaki Morino, Thai Thach Bao, Nguyen Hoaison, Hitoshi Aida, Tadao Saito

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

According to the growth of Internet, an IP(Internet Protocol) router with capacity of terabit/sec is required in the near future. To achieve high capacity, switch fabric should handle many pairs of input ports and output ports. For this purpose, switch of multistage network is required. This paper presents a new scalable multistage packet switch using deflection routing and shortest path routing multistage network. Deflection routing multistage network have advantage of hardware simplicity since switch element has no buffer memory, and variable length packet switching can be easily handled. Furthermore, in the proposed new interconnection method between switch elements, required amount of hardware is reduced compared with conventional switch based on the deflection routing principle. A circuit of 8 × 8 variable length packet switch element is designed on FPGA, and required amount of hardware to realize a 64 × 64 multistage network is calculated. It is shown that 64 × 64 switch will be implemented within one LSI chip, and that 10 Tbps is switch is realized by two-stage interconnection of the LSI chips.

Original languageEnglish
Pages (from-to)2179-2185
Number of pages7
JournalIEEE International Conference on Communications
Volume4
DOIs
Publication statusPublished - 2002 Jan 1

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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