T. Ishitani, K. Tansho, N. Miyahara, S. Kubota, S. Kato
Research output: Contribution to journal › Article › peer-review
A Scarce State Transition Viterbi Decoder VLSI for Bit Error Correction. / Ishitani, T.; Tansho, K.; Miyahara, N.; Kubota, S.; Kato, S.
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TY - JOUR
T1 - A Scarce State Transition Viterbi Decoder VLSI for Bit Error Correction
AU - Ishitani, T.
AU - Tansho, K.
AU - Miyahara, N.
AU - Kubota, S.
AU - Kato, S.
PY - 1987/8/1
Y1 - 1987/8/1
M3 - Article
JO - IEEE Journal of Solid State Circuits
JF - IEEE Journal of Solid State Circuits
ER -