A Scarce-State-Transition Viterbi-Decoder VLSI for Bit Error Correction

Tsunehachi Ishitani, Kazuo Tansho, Norio Miyahara, Shuji Kubota, Shuzo Kato

Research output: Contribution to journalArticle

23 Citations (Scopus)

Abstract

A high-speed Viterbi decoder VLSI with coding rate R = 1/2 and constraint length K = 7 for bit error correction has been developed using 1.5-μm n-well CMOS technology. To reduce both hardware size and power dissipation, a newly developed scarce-state-transition (SST) Viterbi decoding scheme has been employed. In addition, three-layer metallization and an advanced hierarchical macrocell design method (HMCM) have been adopted to improve packing density and reduce chip size. As a result, active chip area has been reduced by half, compared to the conventional standard cell design method (SCM) with two-layer metallization, and 42K gates have been integrated on a chip with a die size of 9.52 x 10.0 mm2. The VLSI decoder has achieved a maximum data throughput rate of 23 Mbit/s with a net coding gain of 4.4 dB (at 10 -4 bit error rate). The chip dissipates only 825 mW at a data rate of 10 Mbit/s.

Original languageEnglish
Pages (from-to)575-582
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume22
Issue number4
DOIs
Publication statusPublished - 1987 Aug

    Fingerprint

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this