TY - JOUR
T1 - A Scarce-State-Transition Viterbi-Decoder VLSI for Bit Error Correction
AU - Ishitani, Tsunehachi
AU - Tansho, Kazuo
AU - Miyahara, Norio
AU - Kubota, Shuji
AU - Kato, Shuzo
N1 - Copyright:
Copyright 2015 Elsevier B.V., All rights reserved.
PY - 1987/8
Y1 - 1987/8
N2 - A high-speed Viterbi decoder VLSI with coding rate R = 1/2 and constraint length K = 7 for bit error correction has been developed using 1.5-μm n-well CMOS technology. To reduce both hardware size and power dissipation, a newly developed scarce-state-transition (SST) Viterbi decoding scheme has been employed. In addition, three-layer metallization and an advanced hierarchical macrocell design method (HMCM) have been adopted to improve packing density and reduce chip size. As a result, active chip area has been reduced by half, compared to the conventional standard cell design method (SCM) with two-layer metallization, and 42K gates have been integrated on a chip with a die size of 9.52 x 10.0 mm2. The VLSI decoder has achieved a maximum data throughput rate of 23 Mbit/s with a net coding gain of 4.4 dB (at 10 -4 bit error rate). The chip dissipates only 825 mW at a data rate of 10 Mbit/s.
AB - A high-speed Viterbi decoder VLSI with coding rate R = 1/2 and constraint length K = 7 for bit error correction has been developed using 1.5-μm n-well CMOS technology. To reduce both hardware size and power dissipation, a newly developed scarce-state-transition (SST) Viterbi decoding scheme has been employed. In addition, three-layer metallization and an advanced hierarchical macrocell design method (HMCM) have been adopted to improve packing density and reduce chip size. As a result, active chip area has been reduced by half, compared to the conventional standard cell design method (SCM) with two-layer metallization, and 42K gates have been integrated on a chip with a die size of 9.52 x 10.0 mm2. The VLSI decoder has achieved a maximum data throughput rate of 23 Mbit/s with a net coding gain of 4.4 dB (at 10 -4 bit error rate). The chip dissipates only 825 mW at a data rate of 10 Mbit/s.
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U2 - 10.1109/JSSC.1987.1052775
DO - 10.1109/JSSC.1987.1052775
M3 - Article
AN - SCOPUS:0023399884
VL - 22
SP - 575
EP - 582
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 4
ER -