A scheme to reduce active leakage power by detecting state transitions

Kimiyoshi Usami, Hiroshi Yoshioka

Research output: Contribution to journalConference article

11 Citations (Scopus)

Abstract

Active leakage power is predicted to become dominant in the total power consumption as the transistor gets scaled. Even in the current technology, dramatic increase of leakage power at elevated temperature is a big problem. Burn-in testing, which is typically performed at 125°C, is facing at difficulties such as throughput degradation of testing due to increase of leakage power. Reducing leakage power at operation time is essential to solve these problems. We propose a novel technique to reduce active leakage power of Finite-State-Machines (FSM's) at run time. Combinational logic gates are dynamically disconnected from the ground to reduce leakage when state transitions do not occur. Simulation results have shown that the proposed scheme reduces active leakage power by 30-60% in 0.1 μm technology. The total power was reduced by 20% at the maximum at 125°C. It was also found that performance degradation was tolerable for burn-in testing.

Original languageEnglish
Pages (from-to)I493-I496
JournalMidwest Symposium on Circuits and Systems
Volume1
Publication statusPublished - 2004 Dec 1
EventThe 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan
Duration: 2004 Jul 252004 Jul 28

Keywords

  • Active leakage
  • Burn-in testing
  • Low-power design
  • Scaling

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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