A study of self-dithering for ΔΣ fractional-N PLL

Yuji Kato, Eri Ioka, Yasuyuki Matsuya

Research output: Research - peer-reviewArticle

Abstract

The ΔΣ fractional-N phase-locked loops (PLL) are being investigated in order to realize a low fractional spurious signal characteristic. In this PLL, the ΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed, and as a result, the limit cycle oscillation increases the spurious signal power. Therefore, a method is required to suppress this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without an external dither generating circuit. The proposed circuit generates dither from the internal signals of the PLL. We simulated the output spectrum of the proposed circuit. The results showed that the proposed circuit suppressed limit cycle oscillation, and that the spurious level of the proposed circuit was almost equal to the spurious level without limit cycle oscillation.

LanguageEnglish
Pages9-14
Number of pages6
JournalElectronics and Communications in Japan
Volume98
Issue number1
DOIs
StatePublished - 2015
Externally publishedYes

Fingerprint

oscillations
Phase locked loops
Networks (circuits)
cycles
Modulators
dithers
modulators
division
output

Keywords

  • Dithering
  • Fractional-N
  • Limit cycle
  • PLL
  • ΔSigma modulator

ASJC Scopus subject areas

  • Signal Processing
  • Physics and Astronomy(all)
  • Computer Networks and Communications
  • Applied Mathematics
  • Electrical and Electronic Engineering

Cite this

A study of self-dithering for ΔΣ fractional-N PLL. / Kato, Yuji; Ioka, Eri; Matsuya, Yasuyuki.

In: Electronics and Communications in Japan, Vol. 98, No. 1, 2015, p. 9-14.

Research output: Research - peer-reviewArticle

Kato, Yuji ; Ioka, Eri ; Matsuya, Yasuyuki. / A study of self-dithering for ΔΣ fractional-N PLL. In: Electronics and Communications in Japan. 2015 ; Vol. 98, No. 1. pp. 9-14
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