Abstract
The ΔΣ fractional-N phase-locked loops (PLL) are being investigated in order to realize a low fractional spurious signal characteristic. In this PLL, the ΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed, and as a result, the limit cycle oscillation increases the spurious signal power. Therefore, a method is required to suppress this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without an external dither generating circuit. The proposed circuit generates dither from the internal signals of the PLL. We simulated the output spectrum of the proposed circuit. The results showed that the proposed circuit suppressed limit cycle oscillation, and that the spurious level of the proposed circuit was almost equal to the spurious level without limit cycle oscillation.
| Language | English |
|---|---|
| Pages | 9-14 |
| Number of pages | 6 |
| Journal | Electronics and Communications in Japan |
| Volume | 98 |
| Issue number | 1 |
| DOIs | |
| State | Published - 2015 |
| Externally published | Yes |
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Keywords
- Dithering
- Fractional-N
- Limit cycle
- PLL
- ΔSigma modulator
ASJC Scopus subject areas
- Signal Processing
- Physics and Astronomy(all)
- Computer Networks and Communications
- Applied Mathematics
- Electrical and Electronic Engineering
Cite this
A study of self-dithering for ΔΣ fractional-N PLL. / Kato, Yuji; Ioka, Eri; Matsuya, Yasuyuki.
In: Electronics and Communications in Japan, Vol. 98, No. 1, 2015, p. 9-14.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A study of self-dithering for ΔΣ fractional-N PLL
AU - Kato,Yuji
AU - Ioka,Eri
AU - Matsuya,Yasuyuki
PY - 2015
Y1 - 2015
N2 - The ΔΣ fractional-N phase-locked loops (PLL) are being investigated in order to realize a low fractional spurious signal characteristic. In this PLL, the ΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed, and as a result, the limit cycle oscillation increases the spurious signal power. Therefore, a method is required to suppress this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without an external dither generating circuit. The proposed circuit generates dither from the internal signals of the PLL. We simulated the output spectrum of the proposed circuit. The results showed that the proposed circuit suppressed limit cycle oscillation, and that the spurious level of the proposed circuit was almost equal to the spurious level without limit cycle oscillation.
AB - The ΔΣ fractional-N phase-locked loops (PLL) are being investigated in order to realize a low fractional spurious signal characteristic. In this PLL, the ΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed, and as a result, the limit cycle oscillation increases the spurious signal power. Therefore, a method is required to suppress this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without an external dither generating circuit. The proposed circuit generates dither from the internal signals of the PLL. We simulated the output spectrum of the proposed circuit. The results showed that the proposed circuit suppressed limit cycle oscillation, and that the spurious level of the proposed circuit was almost equal to the spurious level without limit cycle oscillation.
KW - Dithering
KW - Fractional-N
KW - Limit cycle
KW - PLL
KW - ΔSigma modulator
UR - http://www.scopus.com/inward/record.url?scp=84923132664&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84923132664&partnerID=8YFLogxK
U2 - 10.1002/ecj.11606
DO - 10.1002/ecj.11606
M3 - Article
VL - 98
SP - 9
EP - 14
JO - Electronics and Communications in Japan
T2 - Electronics and Communications in Japan
JF - Electronics and Communications in Japan
SN - 1942-9533
IS - 1
ER -