A study of self-dithering for ΔΣ fractional-N PLL

Yuji Kato, Eri Ioka, Yasuyuki Matsuya

Research output: Contribution to journalArticle

Abstract

The ΔΣ fractional-N PLL is been researched to realize a low fractional spurious signal characteristic. In this PLL, theΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed. As a result, the limit cycle oscillation increases a spurious signal power. Therefore, some method is required for suppressing this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without the external dither generating circuit. The proposed circuit generates the dither from internal signals of PLL. We simulated the output spectrum of the proposed circuit. As a result, we show that the proposed circuit suppressed the limit cycle oscillation, and that the spurious level of the proposed circuit was almost equals to a spurious level without the limit cycle oscillation.

Original languageEnglish
Pages (from-to)234-238
Number of pages5
JournalIEEJ Transactions on Electronics, Information and Systems
Volume133
Issue number2
DOIs
Publication statusPublished - 2013
Externally publishedYes

Keywords

  • Dithering
  • Fractional-N
  • Limit-cycle
  • PLL
  • ΔΣ modulator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A study of self-dithering for ΔΣ fractional-N PLL'. Together they form a unique fingerprint.

  • Cite this