A study of self-dithering for ΔΣ fractional-N PLL

Yuji Kato, Eri Ioka, Yasuyuki Matsuya

Research output: Contribution to journalArticle

Abstract

The ΔΣ fractional-N PLL is been researched to realize a low fractional spurious signal characteristic. In this PLL, theΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed. As a result, the limit cycle oscillation increases a spurious signal power. Therefore, some method is required for suppressing this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without the external dither generating circuit. The proposed circuit generates the dither from internal signals of PLL. We simulated the output spectrum of the proposed circuit. As a result, we show that the proposed circuit suppressed the limit cycle oscillation, and that the spurious level of the proposed circuit was almost equals to a spurious level without the limit cycle oscillation.

LanguageEnglish
Pages234-238
Number of pages5
JournalIEEJ Transactions on Electronics, Information and Systems
Volume133
Issue number2
DOIs
StatePublished - 2013
Externally publishedYes

Fingerprint

Phase locked loops
Networks (circuits)
Modulators

Keywords

  • Dithering
  • Fractional-N
  • Limit-cycle
  • PLL
  • ΔΣ modulator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A study of self-dithering for ΔΣ fractional-N PLL. / Kato, Yuji; Ioka, Eri; Matsuya, Yasuyuki.

In: IEEJ Transactions on Electronics, Information and Systems, Vol. 133, No. 2, 2013, p. 234-238.

Research output: Contribution to journalArticle

@article{cc86eabe82b849fb9433f5d946e1fbc7,
title = "A study of self-dithering for ΔΣ fractional-N PLL",
abstract = "The ΔΣ fractional-N PLL is been researched to realize a low fractional spurious signal characteristic. In this PLL, theΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed. As a result, the limit cycle oscillation increases a spurious signal power. Therefore, some method is required for suppressing this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without the external dither generating circuit. The proposed circuit generates the dither from internal signals of PLL. We simulated the output spectrum of the proposed circuit. As a result, we show that the proposed circuit suppressed the limit cycle oscillation, and that the spurious level of the proposed circuit was almost equals to a spurious level without the limit cycle oscillation.",
keywords = "Dithering, Fractional-N, Limit-cycle, PLL, ΔΣ modulator",
author = "Yuji Kato and Eri Ioka and Yasuyuki Matsuya",
year = "2013",
doi = "10.1541/ieejeiss.133.234",
language = "English",
volume = "133",
pages = "234--238",
journal = "IEEJ Transactions on Electronics, Information and Systems",
issn = "0385-4221",
publisher = "The Institute of Electrical Engineers of Japan",
number = "2",

}

TY - JOUR

T1 - A study of self-dithering for ΔΣ fractional-N PLL

AU - Kato,Yuji

AU - Ioka,Eri

AU - Matsuya,Yasuyuki

PY - 2013

Y1 - 2013

N2 - The ΔΣ fractional-N PLL is been researched to realize a low fractional spurious signal characteristic. In this PLL, theΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed. As a result, the limit cycle oscillation increases a spurious signal power. Therefore, some method is required for suppressing this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without the external dither generating circuit. The proposed circuit generates the dither from internal signals of PLL. We simulated the output spectrum of the proposed circuit. As a result, we show that the proposed circuit suppressed the limit cycle oscillation, and that the spurious level of the proposed circuit was almost equals to a spurious level without the limit cycle oscillation.

AB - The ΔΣ fractional-N PLL is been researched to realize a low fractional spurious signal characteristic. In this PLL, theΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed. As a result, the limit cycle oscillation increases a spurious signal power. Therefore, some method is required for suppressing this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without the external dither generating circuit. The proposed circuit generates the dither from internal signals of PLL. We simulated the output spectrum of the proposed circuit. As a result, we show that the proposed circuit suppressed the limit cycle oscillation, and that the spurious level of the proposed circuit was almost equals to a spurious level without the limit cycle oscillation.

KW - Dithering

KW - Fractional-N

KW - Limit-cycle

KW - PLL

KW - ΔΣ modulator

UR - http://www.scopus.com/inward/record.url?scp=84874168828&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84874168828&partnerID=8YFLogxK

U2 - 10.1541/ieejeiss.133.234

DO - 10.1541/ieejeiss.133.234

M3 - Article

VL - 133

SP - 234

EP - 238

JO - IEEJ Transactions on Electronics, Information and Systems

T2 - IEEJ Transactions on Electronics, Information and Systems

JF - IEEJ Transactions on Electronics, Information and Systems

SN - 0385-4221

IS - 2

ER -