In order to evaluate the radiated emission generating from LSI chip, package, wiring pattern on a printed circuit board (PCB), a programmably controllable test chip is required as a generic noise source. A CMOS gate array was fabricated in a 0.35 um silicon process technology. Both I/O buffer circuits and internal core logic circuits were incorporated as noise generating circuits. The test chip was housed in a quad flat package (QFP) with 304 I/O pins. An evaluation board was designed to verify the functionality of the developed LSI and to measure the switching noise and the magnetic near field. The switching noise and radiated emission noise were observed by stimulating the I/O buffer circuits or internal core logic circuits. The developed test chip was confirmed to be effective to investigate the noise contribution factors at the chip/package-level, and it will be applied to study the radiation noise mechanism at a printed circuit board, or at a system-level packaging environment.
|Number of pages||5|
|Journal||IEEE International Symposium on Electromagnetic Compatibility|
|Publication status||Published - 2001 Jan 1|
ASJC Scopus subject areas
- Condensed Matter Physics
- Electrical and Electronic Engineering