An energy-efficient floorplan driven high-level synthesis algorithm for multiple clock domains design

Shin Ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

Research output: Contribution to journalArticle

1 Citation (Scopus)


In this paper, we first propose an HDR-mcd architecture, which integrates periodically all-in-phase based multiple clock domains and multi-cycle interconnect communication into high-level synthesis. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay should be considered during high-level synthesis. Next, we propose a high-level synthesis algorithm for HDR-mcd, which can reduce energy consumption by optimizing configuration and placement of huddles. Experimental results show that the proposed method achieves 32.5% energy-saving compared with the existing single clock domain based methods

Original languageEnglish
Pages (from-to)1376-1391
Number of pages16
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number7
Publication statusPublished - 2015 Jul 1



  • Energy-optimization
  • High-level synthesis
  • Interconnection delay
  • Multiple clock domains

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Graphics and Computer-Aided Design
  • Applied Mathematics
  • Signal Processing

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