An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Shin Ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture) that integrates dynamic multiple supply voltages and interconnection delays into high-level synthesis. Next, we propose a high-level synthesis algorithm for AVHDR architectures. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which abstracts modules placed close to each other, are naturally generated using floorplanning. Low-supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Experimental results show that our algorithm achieves 50% energy-saving compared with conventional algorithms.

Original languageEnglish
Title of host publication2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs
Publication statusPublished - 2013
Event2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu
Duration: 2013 Apr 222013 Apr 24

Other

Other2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
CityHsinchu
Period13/4/2213/4/24

Fingerprint

Electric potential
Energy conservation
Scheduling
High level synthesis

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M., & Togawa, N. (2013). An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 [6533808] https://doi.org/10.1109/VLDI-DAT.2013.6533808

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. / Abe, Shin Ya; Shi, Youhua; Usami, Kimiyoshi; Yanagisawa, Masao; Togawa, Nozomu.

2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 2013. 6533808.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abe, SY, Shi, Y, Usami, K, Yanagisawa, M & Togawa, N 2013, An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. in 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013., 6533808, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, 13/4/22. https://doi.org/10.1109/VLDI-DAT.2013.6533808
Abe SY, Shi Y, Usami K, Yanagisawa M, Togawa N. An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 2013. 6533808 https://doi.org/10.1109/VLDI-DAT.2013.6533808
Abe, Shin Ya ; Shi, Youhua ; Usami, Kimiyoshi ; Yanagisawa, Masao ; Togawa, Nozomu. / An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 2013.
@inproceedings{32676cb676004fb2b2980079e5b32c8a,
title = "An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages",
abstract = "In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture) that integrates dynamic multiple supply voltages and interconnection delays into high-level synthesis. Next, we propose a high-level synthesis algorithm for AVHDR architectures. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which abstracts modules placed close to each other, are naturally generated using floorplanning. Low-supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Experimental results show that our algorithm achieves 50{\%} energy-saving compared with conventional algorithms.",
author = "Abe, {Shin Ya} and Youhua Shi and Kimiyoshi Usami and Masao Yanagisawa and Nozomu Togawa",
year = "2013",
doi = "10.1109/VLDI-DAT.2013.6533808",
language = "English",
isbn = "9781467344357",
booktitle = "2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013",

}

TY - GEN

T1 - An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

AU - Abe, Shin Ya

AU - Shi, Youhua

AU - Usami, Kimiyoshi

AU - Yanagisawa, Masao

AU - Togawa, Nozomu

PY - 2013

Y1 - 2013

N2 - In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture) that integrates dynamic multiple supply voltages and interconnection delays into high-level synthesis. Next, we propose a high-level synthesis algorithm for AVHDR architectures. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which abstracts modules placed close to each other, are naturally generated using floorplanning. Low-supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Experimental results show that our algorithm achieves 50% energy-saving compared with conventional algorithms.

AB - In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture) that integrates dynamic multiple supply voltages and interconnection delays into high-level synthesis. Next, we propose a high-level synthesis algorithm for AVHDR architectures. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which abstracts modules placed close to each other, are naturally generated using floorplanning. Low-supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Experimental results show that our algorithm achieves 50% energy-saving compared with conventional algorithms.

UR - http://www.scopus.com/inward/record.url?scp=84881335853&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84881335853&partnerID=8YFLogxK

U2 - 10.1109/VLDI-DAT.2013.6533808

DO - 10.1109/VLDI-DAT.2013.6533808

M3 - Conference contribution

SN - 9781467344357

BT - 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

ER -