TY - GEN
T1 - An SoC platform with on-chip web interface for in-field monitoring
AU - Iizuka, Tetsuya
AU - Nakamura, Daisuke
AU - Yoshida, Hiroaki
AU - Komatsu, Satoshi
AU - Sasaki, Masahiro
AU - Ikeda, Makoto
AU - Asada, Kunihiro
PY - 2009/12/1
Y1 - 2009/12/1
N2 - As the VLSI technologies scale down to the nanometer regime, the circuit design and verification processes have become more and more complex and a reliable operation of VLSI becomes sensitive to the PVT (Process, Voltage, and Temperature) variations. Therefore, the LSI test only before the shipment to screen out the initial failures has been insufficient to ensure the reliable in-field operation of LSI. In this paper, we propose an SoC platform with on-chip web interface to realize an in-field LSI testing and an easy access to the on-chip LSI monitoring circuits such as scan registers, temperature sensors, and so on. We can control the on-chip monitoring systems through the web interface, and can monitor the LSI correct operations from remote locations using the proposed platform. Therefore, the proposed SoC platform realizes the LSI functionality monitoring even after the shipment and can test the in-field operation of LSI. This platform consists of 16-bit CPU, 64K words of instruction/data memory, and 10Base-T ethernet interface. A preliminary version of the proposed platform was implemented on 0.18μm standard CMOS process. The area overhead is 8.44mm2 on 0.18μm process, and is estimated to scale down to about 1mm2 on 65nm process.
AB - As the VLSI technologies scale down to the nanometer regime, the circuit design and verification processes have become more and more complex and a reliable operation of VLSI becomes sensitive to the PVT (Process, Voltage, and Temperature) variations. Therefore, the LSI test only before the shipment to screen out the initial failures has been insufficient to ensure the reliable in-field operation of LSI. In this paper, we propose an SoC platform with on-chip web interface to realize an in-field LSI testing and an easy access to the on-chip LSI monitoring circuits such as scan registers, temperature sensors, and so on. We can control the on-chip monitoring systems through the web interface, and can monitor the LSI correct operations from remote locations using the proposed platform. Therefore, the proposed SoC platform realizes the LSI functionality monitoring even after the shipment and can test the in-field operation of LSI. This platform consists of 16-bit CPU, 64K words of instruction/data memory, and 10Base-T ethernet interface. A preliminary version of the proposed platform was implemented on 0.18μm standard CMOS process. The area overhead is 8.44mm2 on 0.18μm process, and is estimated to scale down to about 1mm2 on 65nm process.
UR - http://www.scopus.com/inward/record.url?scp=77951483759&partnerID=8YFLogxK
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U2 - 10.1109/SOCDC.2009.5423911
DO - 10.1109/SOCDC.2009.5423911
M3 - Conference contribution
AN - SCOPUS:77951483759
SN - 9781424450343
T3 - 2009 International SoC Design Conference, ISOCC 2009
SP - 208
EP - 211
BT - 2009 International SoC Design Conference, ISOCC 2009
T2 - 2009 International SoC Design Conference, ISOCC 2009
Y2 - 22 November 2009 through 24 November 2009
ER -