An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)

Tadashi Maeda, Keiichi Numata, Masahiro Fujii, Masatoshi Tokushima, Shigeki Wada, Muneo Fukaishi, Masaoki Ishikawa

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FF's. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers.

Original languageEnglish
Pages (from-to)1361-1363
Number of pages3
JournalIEEE Journal of Solid-State Circuits
Volume31
Issue number9
DOIs
Publication statusPublished - 1996 Sep
Externally publishedYes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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