Abstract
The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FF's. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers.
| Original language | English |
|---|---|
| Pages (from-to) | 1361-1363 |
| Number of pages | 3 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 31 |
| Issue number | 9 |
| DOIs | |
| Publication status | Published - 1996 Sep |
| Externally published | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF). / Maeda, Tadashi; Numata, Keiichi; Fujii, Masahiro; Tokushima, Masatoshi; Wada, Shigeki; Fukaishi, Muneo; Ishikawa, Masaoki.
In: IEEE Journal of Solid-State Circuits, Vol. 31, No. 9, 09.1996, p. 1361-1363.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)
AU - Maeda, Tadashi
AU - Numata, Keiichi
AU - Fujii, Masahiro
AU - Tokushima, Masatoshi
AU - Wada, Shigeki
AU - Fukaishi, Muneo
AU - Ishikawa, Masaoki
PY - 1996/9
Y1 - 1996/9
N2 - The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FF's. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers.
AB - The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FF's. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers.
UR - http://www.scopus.com/inward/record.url?scp=0030242774&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0030242774&partnerID=8YFLogxK
U2 - 10.1109/4.535426
DO - 10.1109/4.535426
M3 - Article
AN - SCOPUS:0030242774
VL - 31
SP - 1361
EP - 1363
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 9
ER -