Abstract
The developed GaAs static flip-flop operates at a data rate of 10 Gb/s with a power consumption of 2.8 mW at a supply voltage of 0.6 V. The power consumption at 10 Gb/s is 1/3 that of the lowest reported value for D-FF's. A divider using the QD-FF configuration operates at a clock frequency of 16 GHz with a power consumption of 2.4 mW at a supply voltage of 0.6 V. The power-delay product is about one-third that of the lowest reported value for dividers.
Original language | English |
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Pages (from-to) | 1361-1363 |
Number of pages | 3 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 31 |
Issue number | 9 |
DOIs | |
Publication status | Published - 1996 Sep 1 |
Externally published | Yes |
ASJC Scopus subject areas
- Electrical and Electronic Engineering