Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP

Hiroki Takatani; Yosuke Tanaka; Haruya Fujita; Yoshiaki Oizono; Yoshitaka Nabeshima; Toshio Sudo; Atsushi Sakai; Shiro Uchiyama; Hiroaki Ikeda

doi:10.1109/EDAPS.2012.6469419

Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP

Hiroki Takatani, Yosuke Tanaka, Haruya Fujita, Yoshiaki Oizono, Yoshitaka Nabeshima, Toshio Sudo, Atsushi Sakai, Shiro Uchiyama, Hiroaki Ikeda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure. The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.

Original language	English
Title of host publication	2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
Pages	185-188
Number of pages	4
DOIs	https://doi.org/10.1109/EDAPS.2012.6469419
Publication status	Published - 2012 Dec 1
Event	2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 - Taipei, Taiwan, Province of China Duration: 2012 Dec 9 → 2012 Dec 11

Publication series

Name	2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012

Conference

Conference	2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
Country/Territory	Taiwan, Province of China
City	Taipei
Period	12/12/9 → 12/12/11

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/EDAPS.2012.6469419

Cite this

Takatani, H., Tanaka, Y., Fujita, H., Oizono, Y., Nabeshima, Y., Sudo, T., Sakai, A., Uchiyama, S., & Ikeda, H. (2012). Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP. In 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 (pp. 185-188). [6469419] (2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012). https://doi.org/10.1109/EDAPS.2012.6469419

Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP. / Takatani, Hiroki; Tanaka, Yosuke; Fujita, Haruya et al.

2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. p. 185-188 6469419 (2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Takatani, H, Tanaka, Y, Fujita, H, Oizono, Y, Nabeshima, Y, Sudo, T, Sakai, A, Uchiyama, S & Ikeda, H 2012, Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP. in 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012., 6469419, 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012, pp. 185-188, 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012, Taipei, Taiwan, Province of China, 12/12/9. https://doi.org/10.1109/EDAPS.2012.6469419

Takatani H, Tanaka Y, Fujita H, Oizono Y, Nabeshima Y, Sudo T et al. Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP. In 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. p. 185-188. 6469419. (2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012). doi: 10.1109/EDAPS.2012.6469419

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abstract = "The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure. The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.",

author = "Hiroki Takatani and Yosuke Tanaka and Haruya Fujita and Yoshiaki Oizono and Yoshitaka Nabeshima and Toshio Sudo and Atsushi Sakai and Shiro Uchiyama and Hiroaki Ikeda",

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AU - Nabeshima, Yoshitaka

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AU - Sakai, Atsushi

AU - Uchiyama, Shiro

AU - Ikeda, Hiroaki

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N2 - The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure. The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.

AB - The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure. The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.

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Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP

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