Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP

Hiroki Takatani, Yosuke Tanaka, Haruya Fujita, Yoshiaki Oizono, Yoshitaka Nabeshima, Toshio Sudo, Atsushi Sakai, Shiro Uchiyama, Hiroaki Ikeda

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure. The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.

Original languageEnglish
Title of host publication2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
Pages185-188
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 - Taipei
Duration: 2012 Dec 92012 Dec 11

Other

Other2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
CityTaipei
Period12/12/912/12/11

Fingerprint

Electric power distribution
Silicon
Substrates
Data storage equipment
System-in-package

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Takatani, H., Tanaka, Y., Fujita, H., Oizono, Y., Nabeshima, Y., Sudo, T., ... Ikeda, H. (2012). Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP. In 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 (pp. 185-188). [6469419] https://doi.org/10.1109/EDAPS.2012.6469419

Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP. / Takatani, Hiroki; Tanaka, Yosuke; Fujita, Haruya; Oizono, Yoshiaki; Nabeshima, Yoshitaka; Sudo, Toshio; Sakai, Atsushi; Uchiyama, Shiro; Ikeda, Hiroaki.

2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. p. 185-188 6469419.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Takatani, H, Tanaka, Y, Fujita, H, Oizono, Y, Nabeshima, Y, Sudo, T, Sakai, A, Uchiyama, S & Ikeda, H 2012, Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP. in 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012., 6469419, pp. 185-188, 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012, Taipei, 12/12/9. https://doi.org/10.1109/EDAPS.2012.6469419
Takatani H, Tanaka Y, Fujita H, Oizono Y, Nabeshima Y, Sudo T et al. Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP. In 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. p. 185-188. 6469419 https://doi.org/10.1109/EDAPS.2012.6469419
Takatani, Hiroki ; Tanaka, Yosuke ; Fujita, Haruya ; Oizono, Yoshiaki ; Nabeshima, Yoshitaka ; Sudo, Toshio ; Sakai, Atsushi ; Uchiyama, Shiro ; Ikeda, Hiroaki. / Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP. 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. pp. 185-188
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