Analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

Akira Wakabayashi, Yasutaka Mitani, Kazushige Horio

Research output: Contribution to journalArticle

20 Citations (Scopus)

Abstract

Two-dimensional analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs is performed, and their dependence on the structural parameters and the off-state gate voltage V Goff is studied. It is shown that when V Goff is around the threshold voltage (pinchoff voltage) V th, the gate-lag could be almost eliminated by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when V Goff is much more negative than V th.

Original languageEnglish
Pages (from-to)37-41
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume49
Issue number1
DOIs
Publication statusPublished - 2002 Jan

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time lag
field effect transistors
Electric potential
Threshold voltage
dimensional analysis
electric potential
gallium arsenide
threshold voltage

Keywords

  • Buried-gate structure
  • GaAs MESFET
  • Gate lag
  • Recessed-gate structure
  • Surface state
  • Two-dimensional simulation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

Cite this

Analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs. / Wakabayashi, Akira; Mitani, Yasutaka; Horio, Kazushige.

In: IEEE Transactions on Electron Devices, Vol. 49, No. 1, 01.2002, p. 37-41.

Research output: Contribution to journalArticle

@article{189b3568bd4047dcb7218a21529dabff,
title = "Analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs",
abstract = "Two-dimensional analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs is performed, and their dependence on the structural parameters and the off-state gate voltage V Goff is studied. It is shown that when V Goff is around the threshold voltage (pinchoff voltage) V th, the gate-lag could be almost eliminated by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when V Goff is much more negative than V th.",
keywords = "Buried-gate structure, GaAs MESFET, Gate lag, Recessed-gate structure, Surface state, Two-dimensional simulation",
author = "Akira Wakabayashi and Yasutaka Mitani and Kazushige Horio",
year = "2002",
month = "1",
doi = "10.1109/16.974746",
language = "English",
volume = "49",
pages = "37--41",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",

}

TY - JOUR

T1 - Analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

AU - Wakabayashi, Akira

AU - Mitani, Yasutaka

AU - Horio, Kazushige

PY - 2002/1

Y1 - 2002/1

N2 - Two-dimensional analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs is performed, and their dependence on the structural parameters and the off-state gate voltage V Goff is studied. It is shown that when V Goff is around the threshold voltage (pinchoff voltage) V th, the gate-lag could be almost eliminated by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when V Goff is much more negative than V th.

AB - Two-dimensional analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs is performed, and their dependence on the structural parameters and the off-state gate voltage V Goff is studied. It is shown that when V Goff is around the threshold voltage (pinchoff voltage) V th, the gate-lag could be almost eliminated by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when V Goff is much more negative than V th.

KW - Buried-gate structure

KW - GaAs MESFET

KW - Gate lag

KW - Recessed-gate structure

KW - Surface state

KW - Two-dimensional simulation

UR - http://www.scopus.com/inward/record.url?scp=0036253280&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036253280&partnerID=8YFLogxK

U2 - 10.1109/16.974746

DO - 10.1109/16.974746

M3 - Article

VL - 49

SP - 37

EP - 41

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 1

ER -