Analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

Akira Wakabayashi, Yasutaka Mitani, Kazushige Horio

Research output: Contribution to journalArticle

20 Citations (Scopus)

Abstract

Two-dimensional analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs is performed, and their dependence on the structural parameters and the off-state gate voltage V Goff is studied. It is shown that when V Goff is around the threshold voltage (pinchoff voltage) V th, the gate-lag could be almost eliminated by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when V Goff is much more negative than V th.

Original languageEnglish
Pages (from-to)37-41
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume49
Issue number1
DOIs
Publication statusPublished - 2002 Jan 1

Keywords

  • Buried-gate structure
  • GaAs MESFET
  • Gate lag
  • Recessed-gate structure
  • Surface state
  • Two-dimensional simulation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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