Analysis of surface-state effects on gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

K. Horio, A. Wakabayashi, T. Yamada

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

Gate-lag or slow current transient in GaAs MESFETs is studied by two-dimensional analysis including surface-state effects. It is shown that in a recessed-gate structure, the gate-lag is reduced to some extent by increasing the recess depth, but it may not be so much suppressed as expected because the surface states around the gate affect the turn-on characteristics. However, by introducing the buried-gate structure where the gate electrode is attached to the vertical planes of the recess and (also) to the same planes as the drain electrode, the surface-state effects are minimized, and the gate-lag can be greatly reduced.

Original languageEnglish
Pages191-194
Number of pages4
DOIs
Publication statusPublished - 1999
EventProceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits - Singapore, Singapore
Duration: 1999 Jul 51999 Jul 9

Other

OtherProceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits
CitySingapore, Singapore
Period99/7/599/7/9

ASJC Scopus subject areas

  • Engineering(all)

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    Horio, K., Wakabayashi, A., & Yamada, T. (1999). Analysis of surface-state effects on gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs. 191-194. Paper presented at Proceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits, Singapore, Singapore, . https://doi.org/10.1109/ipfa.1999.791332