Analytical expression of quantization noise in time-to-digital converter based on the fourier series analysis

Tadashi Maeda, Takashi Tokairin

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

This paper describes a simple, analytical expression for quantization noise in a time-to-digital converter (TDC) based on Fourier-series analysis. We analyzed inverter propagation-delay variations due to fluctuations in the threshold voltage, and here we also discuss phase noise in an all-digital phase locked loop (ADPLL). The large standard deviation in the threshold voltage degrades phase noise even under short inverter-delay conditions. Increasing the gate area of transistors led to low phase noise due to threshold variations, but greatly increased power consumption. The paper also discusses TDC power reduction method without degrading quantization noise. Our analytically predicted results agreed well with the data obtained from a Spectre-RF simulator.

Original languageEnglish
Article number5371917
Pages (from-to)1538-1548
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume57
Issue number7
DOIs
Publication statusPublished - 2010 Jan 6
Externally publishedYes

Keywords

  • Digitally controlled oscillator
  • Fourier series expansion
  • Gaussian distribution
  • frequency synthesizer
  • phase noise
  • quantization noise
  • sinusoidal analysis
  • time-to-digital converter

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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