Analytical expression of quantization noise in time-to-digital converter based on the fourier series analysis

Tadashi Maeda, Takashi Tokairin

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

This paper describes a simple, analytical expression for quantization noise in a time-to-digital converter (TDC) based on Fourier-series analysis. We analyzed inverter propagation-delay variations due to fluctuations in the threshold voltage, and here we also discuss phase noise in an all-digital phase locked loop (ADPLL). The large standard deviation in the threshold voltage degrades phase noise even under short inverter-delay conditions. Increasing the gate area of transistors led to low phase noise due to threshold variations, but greatly increased power consumption. The paper also discusses TDC power reduction method without degrading quantization noise. Our analytically predicted results agreed well with the data obtained from a Spectre-RF simulator.

Original languageEnglish
Article number5371917
Pages (from-to)1538-1548
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume57
Issue number7
DOIs
Publication statusPublished - 2010
Externally publishedYes

Fingerprint

Fourier series
Phase noise
Threshold voltage
Power converters
Phase locked loops
Transistors
Electric power utilization
Simulators

Keywords

  • Digitally controlled oscillator
  • Fourier series expansion
  • frequency synthesizer
  • Gaussian distribution
  • phase noise
  • quantization noise
  • sinusoidal analysis
  • time-to-digital converter

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Analytical expression of quantization noise in time-to-digital converter based on the fourier series analysis. / Maeda, Tadashi; Tokairin, Takashi.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 57, No. 7, 5371917, 2010, p. 1538-1548.

Research output: Contribution to journalArticle

@article{5a790f04e6a14575a634a412443eded2,
title = "Analytical expression of quantization noise in time-to-digital converter based on the fourier series analysis",
abstract = "This paper describes a simple, analytical expression for quantization noise in a time-to-digital converter (TDC) based on Fourier-series analysis. We analyzed inverter propagation-delay variations due to fluctuations in the threshold voltage, and here we also discuss phase noise in an all-digital phase locked loop (ADPLL). The large standard deviation in the threshold voltage degrades phase noise even under short inverter-delay conditions. Increasing the gate area of transistors led to low phase noise due to threshold variations, but greatly increased power consumption. The paper also discusses TDC power reduction method without degrading quantization noise. Our analytically predicted results agreed well with the data obtained from a Spectre-RF simulator.",
keywords = "Digitally controlled oscillator, Fourier series expansion, frequency synthesizer, Gaussian distribution, phase noise, quantization noise, sinusoidal analysis, time-to-digital converter",
author = "Tadashi Maeda and Takashi Tokairin",
year = "2010",
doi = "10.1109/TCSI.2009.2035411",
language = "English",
volume = "57",
pages = "1538--1548",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1057-7122",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "7",

}

TY - JOUR

T1 - Analytical expression of quantization noise in time-to-digital converter based on the fourier series analysis

AU - Maeda, Tadashi

AU - Tokairin, Takashi

PY - 2010

Y1 - 2010

N2 - This paper describes a simple, analytical expression for quantization noise in a time-to-digital converter (TDC) based on Fourier-series analysis. We analyzed inverter propagation-delay variations due to fluctuations in the threshold voltage, and here we also discuss phase noise in an all-digital phase locked loop (ADPLL). The large standard deviation in the threshold voltage degrades phase noise even under short inverter-delay conditions. Increasing the gate area of transistors led to low phase noise due to threshold variations, but greatly increased power consumption. The paper also discusses TDC power reduction method without degrading quantization noise. Our analytically predicted results agreed well with the data obtained from a Spectre-RF simulator.

AB - This paper describes a simple, analytical expression for quantization noise in a time-to-digital converter (TDC) based on Fourier-series analysis. We analyzed inverter propagation-delay variations due to fluctuations in the threshold voltage, and here we also discuss phase noise in an all-digital phase locked loop (ADPLL). The large standard deviation in the threshold voltage degrades phase noise even under short inverter-delay conditions. Increasing the gate area of transistors led to low phase noise due to threshold variations, but greatly increased power consumption. The paper also discusses TDC power reduction method without degrading quantization noise. Our analytically predicted results agreed well with the data obtained from a Spectre-RF simulator.

KW - Digitally controlled oscillator

KW - Fourier series expansion

KW - frequency synthesizer

KW - Gaussian distribution

KW - phase noise

KW - quantization noise

KW - sinusoidal analysis

KW - time-to-digital converter

UR - http://www.scopus.com/inward/record.url?scp=77954862644&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77954862644&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2009.2035411

DO - 10.1109/TCSI.2009.2035411

M3 - Article

AN - SCOPUS:77954862644

VL - 57

SP - 1538

EP - 1548

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1057-7122

IS - 7

M1 - 5371917

ER -