Asymmetric sidewall process for high performance LDD MOSFET's

Tadahiko Horiuchi, Tetsuya Homma, Yukinobu Murao, Koichiro Okumura

Research output: Contribution to journalArticle

30 Citations (Scopus)

Abstract

An asymmetric LDD sidewall spacer technology is presented which gives a high drivability of LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated by using a selective oxide deposition technique. The process implemented in a CMOS fabrication sequence requires no additional masking step. The fact that no reliability problems are introduced in the transistor characteristics by the selective oxide deposition process is also examined.

Original languageEnglish
Pages (from-to)186-190
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume41
Issue number2
DOIs
Publication statusPublished - 1994 Feb
Externally publishedYes

Fingerprint

spacers
Oxides
field effect transistors
Hot carriers
oxides
immunity
masking
CMOS
Transistors
transistors
Fabrication
fabrication

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

Cite this

Asymmetric sidewall process for high performance LDD MOSFET's. / Horiuchi, Tadahiko; Homma, Tetsuya; Murao, Yukinobu; Okumura, Koichiro.

In: IEEE Transactions on Electron Devices, Vol. 41, No. 2, 02.1994, p. 186-190.

Research output: Contribution to journalArticle

Horiuchi, Tadahiko ; Homma, Tetsuya ; Murao, Yukinobu ; Okumura, Koichiro. / Asymmetric sidewall process for high performance LDD MOSFET's. In: IEEE Transactions on Electron Devices. 1994 ; Vol. 41, No. 2. pp. 186-190.
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