Asymmetric sidewall process for high performance LDD MOSFET's

Tadahiko Horiuchi, Tetsuya Homma, Yukinobu Murao, Koichiro Okumura

Research output: Contribution to journalArticlepeer-review

28 Citations (Scopus)


An asymmetric LDD sidewall spacer technology is presented which gives a high drivability of LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated by using a selective oxide deposition technique. The process implemented in a CMOS fabrication sequence requires no additional masking step. The fact that no reliability problems are introduced in the transistor characteristics by the selective oxide deposition process is also examined.

Original languageEnglish
Pages (from-to)186-190
Number of pages5
JournalIEEE Transactions on Electron Devices
Issue number2
Publication statusPublished - 1994 Feb 1
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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