Asymmetric sidewall process for high performance LDD MOSFET's

Tadahiko Horiuchi; Tetsuya Homma; Yukinobu Murao; Koichiro Okumura

doi:10.1109/16.277381

Asymmetric sidewall process for high performance LDD MOSFET's

Tadahiko Horiuchi, Tetsuya Homma, Yukinobu Murao, Koichiro Okumura

Research output: Contribution to journal › Article › peer-review

28 Citations (Scopus)

Abstract

An asymmetric LDD sidewall spacer technology is presented which gives a high drivability of LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated by using a selective oxide deposition technique. The process implemented in a CMOS fabrication sequence requires no additional masking step. The fact that no reliability problems are introduced in the transistor characteristics by the selective oxide deposition process is also examined.

Original language	English
Pages (from-to)	186-190
Number of pages	5
Journal	IEEE Transactions on Electron Devices
Volume	41
Issue number	2
DOIs	https://doi.org/10.1109/16.277381
Publication status	Published - 1994 Feb 1
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/16.277381

Cite this

@article{4511b22f95de4ee5a4e8f2ee5b2c4e3c,

title = "Asymmetric sidewall process for high performance LDD MOSFET's",

abstract = "An asymmetric LDD sidewall spacer technology is presented which gives a high drivability of LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated by using a selective oxide deposition technique. The process implemented in a CMOS fabrication sequence requires no additional masking step. The fact that no reliability problems are introduced in the transistor characteristics by the selective oxide deposition process is also examined.",

author = "Tadahiko Horiuchi and Tetsuya Homma and Yukinobu Murao and Koichiro Okumura",

year = "1994",

month = feb,

day = "1",

doi = "10.1109/16.277381",

language = "English",

volume = "41",

pages = "186--190",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - Asymmetric sidewall process for high performance LDD MOSFET's

AU - Horiuchi, Tadahiko

AU - Homma, Tetsuya

AU - Murao, Yukinobu

AU - Okumura, Koichiro

PY - 1994/2/1

Y1 - 1994/2/1

N2 - An asymmetric LDD sidewall spacer technology is presented which gives a high drivability of LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated by using a selective oxide deposition technique. The process implemented in a CMOS fabrication sequence requires no additional masking step. The fact that no reliability problems are introduced in the transistor characteristics by the selective oxide deposition process is also examined.

AB - An asymmetric LDD sidewall spacer technology is presented which gives a high drivability of LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated by using a selective oxide deposition technique. The process implemented in a CMOS fabrication sequence requires no additional masking step. The fact that no reliability problems are introduced in the transistor characteristics by the selective oxide deposition process is also examined.

UR - http://www.scopus.com/inward/record.url?scp=0028380786&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028380786&partnerID=8YFLogxK

U2 - 10.1109/16.277381

DO - 10.1109/16.277381

M3 - Article

AN - SCOPUS:0028380786

SN - 0018-9383

VL - 41

SP - 186

EP - 190

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 2

ER -

Asymmetric sidewall process for high performance LDD MOSFET's

Abstract

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this