At 13.56 MHz, the circuit parasitic elements strongly affect the stability, performance, and efficiency of the inverter. In this paper, the effect of parasitic elements in the 13.56-MHz half-bridge inverter is analyzed in detail based on the point of view of the high-frequency ringing in the circuit. A proposed inverter design that aims to attenuate the influence of the parasitic elements is presented, including optimized printed circuit board (PCB) design and ringing damping design. The simulation and experiment results show that the proposed PCB design not only reduces the parasitic inductance in the ringing loop but also improves the stability of the inverter by avoiding the subresonant at low frequency and reducing the radiation electromagnetic interference noise. This paper also points out that the ringing current exists in the circuit even with the proposed optimized PCB design lead to the instability of the inverter at high voltage operating condition. The proposed damping circuit significantly suppresses the ringing in the circuit and improves the stability as well as the efficiency of the inverter. The experiment results confirm that by using the proposed design, the half-bridge inverter module using Silicon mosfet is stable at 13.56-MHz switching frequency and its efficiency obtains text93.1% at 1.2-kW output power.
- 13.56-MHz inverter
- Class D inverter
- high-frequency inverter
- wireless power transfer
- wireless power transfer (WPT)
ASJC Scopus subject areas
- Electrical and Electronic Engineering