Automated low-power technique exploiting multiple supply voltages applied to a media processor

Kimiyoshi Usami; Kazutaka Nogami; Mutsunori Igarashi; Fumihiro Minami; Yukio Kawasaki; Takashi Ishikawa; Masahiro Kanazawa; Takahiro Aoki; Midori Takano; Chiharu Mizuno; Makoto Ichida; Shinji Sonoda; Makoto Takahashi; Naoyuki Hatanaka

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Kimiyoshi Usami, Kazutaka Nogami, Mutsunori Igarashi, Fumihiro Minami, Yukio Kawasaki, Takashi Ishikawa, Masahiro Kanazawa, Takahiro Aoki, Midori Takano, Chiharu Mizuno, Makoto Ichida, Shinji Sonoda, Makoto Takahashi, Naoyuki Hatanaka

Research output: Contribution to journal › Conference article › peer-review

22 Citations (Scopus)

Abstract

This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. Combining these techniques together, we applied it to the random logic modules of a media processor chip. The combined technique reduced the power by 47% on average with an area overhead of 15% at the random logic, while keeping the performance.

Original language	English
Pages (from-to)	131-134
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 1997
Externally published	Yes
Event	Proceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: 1997 May 5 → 1997 May 8

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Automated low-power technique exploiting multiple supply voltages applied to a media processor",

abstract = "This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. Combining these techniques together, we applied it to the random logic modules of a media processor chip. The combined technique reduced the power by 47% on average with an area overhead of 15% at the random logic, while keeping the performance.",

author = "Kimiyoshi Usami and Kazutaka Nogami and Mutsunori Igarashi and Fumihiro Minami and Yukio Kawasaki and Takashi Ishikawa and Masahiro Kanazawa and Takahiro Aoki and Midori Takano and Chiharu Mizuno and Makoto Ichida and Shinji Sonoda and Makoto Takahashi and Naoyuki Hatanaka",

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journal = "Proceedings of the Custom Integrated Circuits Conference",

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note = "Proceedings of the 1997 IEEE Custom Integrated Circuits Conference ; Conference date: 05-05-1997 Through 08-05-1997",

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T1 - Automated low-power technique exploiting multiple supply voltages applied to a media processor

AU - Usami, Kimiyoshi

AU - Nogami, Kazutaka

AU - Igarashi, Mutsunori

AU - Minami, Fumihiro

AU - Kawasaki, Yukio

AU - Ishikawa, Takashi

AU - Kanazawa, Masahiro

AU - Aoki, Takahiro

AU - Takano, Midori

AU - Mizuno, Chiharu

AU - Ichida, Makoto

AU - Sonoda, Shinji

AU - Takahashi, Makoto

AU - Hatanaka, Naoyuki

PY - 1997

Y1 - 1997

N2 - This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. Combining these techniques together, we applied it to the random logic modules of a media processor chip. The combined technique reduced the power by 47% on average with an area overhead of 15% at the random logic, while keeping the performance.

AB - This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. Combining these techniques together, we applied it to the random logic modules of a media processor chip. The combined technique reduced the power by 47% on average with an area overhead of 15% at the random logic, while keeping the performance.

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AN - SCOPUS:0030648681

SN - 0886-5930

SP - 131

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JO - Proceedings of the Custom Integrated Circuits Conference

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T2 - Proceedings of the 1997 IEEE Custom Integrated Circuits Conference

Y2 - 5 May 1997 through 8 May 1997

ER -

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Abstract

ASJC Scopus subject areas

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